Embedded-Logic Multi-Bit Memory Cells With Shared Latches
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Solution Overview
Problem
Designing complex integrated circuits with thousands, millions, or billions of components is excessively time-consuming and costly when done manually, necessitating efficient automation tools to manage component placement and logic implementation.
Innovation Solution
The use of Electronic Design Automation (EDA) tools and standard cell libraries, along with a circuit design engine that includes a circuit analysis and modification engine and a circuit synthesizer, to automate the design process by breaking down the circuit into smaller pieces, optimizing cell usage, and converting high-level designs into lower-level implementations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If manual design methods are used for complex integrated circuits, then design accuracy can be maintained, but design time and cost increase excessively
Solution Approach 1:
The patent segments the integrated circuit design into hierarchical levels (logical layer, physical layout layer, transistor layer). EDA tools operate on these segmented representations to automate design tasks while maintaining accuracy. The segmentation allows complex designs to be managed through standardized cells and modules at different abstraction levels.
Solution Approach 2:
The patent introduces EDA tools as an intermediary between the designer and the physical circuit implementation. These tools serve as a mediator that translates high-level logical designs into detailed physical layouts and transistor arrangements, automating the design process while preserving design intent and accuracy.
2Reliability
If manual design methods are used for complex integrated circuits, then design quality can be controlled, but design cost increases excessively
Solution Approach 1:
The patent enables the design system to serve itself through automated EDA tools that perform layout generation, routing, and verification without requiring manual intervention for every component. The tools automatically handle repetitive tasks, consistency checks, and optimization, reducing both cost and potential human error while maintaining quality standards.
Solution Approach 2:
The patent utilizes standard cell libraries where proven, optimized circuit blocks are created once and then copied and reused multiple times in different designs. This copying approach ensures consistency, reduces design costs, and maintains quality through proven designs while avoiding redundant manual work.
3Productivity
If standard cell libraries and automation tools are used, then design time and cost are reduced, but design complexity increases
Solution Approach 1:
The patent employs universal standard cell libraries that contain multi-functional building blocks capable of performing various logic functions. These standardized cells can be configured and combined to implement different circuit behaviors, reducing the need for custom designs while maintaining productivity. The EDA tools provide universal interfaces for manipulating these cells across different design stages.
Data Source
AI summary
Systems and method are provided that include a standard cell with multiple input and output storage elements, such as flip flops, latches, etc., with some combination logic interconnected between them. In embodiments, the slave latches on input flip flops are replaced with a fewer number latches at a downstream node(s) of the combination logic resulting in improved performance, area and power, while maintaining functionality at the interface pins of the standard cell. The process of inferring such a standard cell from a behavioral description, such as RTL, of a design or remapping equivalent sub-circuits from a netlist to such a standard cell is also described.