Embedded Logic Analyzer for Selective Internal Signal Debugging
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Debugging integrated circuits is inefficient due to the need for many input-output pins to extract internal signals, increasing chip size and degrading productivity, especially when debugging internal logic not connected directly to the main bus.
Innovation Solution
An embedded logic analyzer within the integrated circuit that generates capture data signals and comparison enable signals based on input data, performs logic operations to determine data capture timing, and packs capture data with time information for efficient data extraction, overcoming bus traffic and memory limitations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Difficulty of detecting and measuring
If many input-output pins are assigned to extract internal signals, then internal logic signals can be extracted for debugging, but chip size is increased and productivity is degraded
Solution Approach 1:
The patent merges the logic analyzer functionality with the integrated circuit itself, creating an embedded logic analyzer that shares resources with the main circuit. This integration eliminates the need for separate external debugging equipment and reduces the number of pins required for signal extraction, thereby improving productivity without compromising debugging capability
Solution Approach 2:
The embedded logic analyzer is designed to perform multiple functions: it can capture internal logic signals, store them in buffer memory, and transfer them to external devices when needed. This multi-functionality allows the same hardware structure to serve both normal circuit operation and debugging purposes, reducing the need for dedicated debugging pins
2Difficulty of detecting and measuring
If many input-output pins are assigned to extract internal signals, then internal logic signals can be extracted for debugging, but chip size is increased
Solution Approach 1:
The logic analyzer is merged into the integrated circuit chip itself, sharing physical space and resources with the main circuit functionality. This integration allows the debugging functionality to be implemented using existing chip area rather than requiring additional external pins and separate debugging equipment, thereby preventing chip area expansion
Solution Approach 2:
The embedded logic analyzer is nested within the integrated circuit structure, with its components (comparison blocks, operation blocks, packer circuitry, buffer memory) integrated into the chip's existing architecture. This nesting approach allows the debugging functionality to be housed within the same physical boundaries as the main circuit, avoiding any increase in chip area
3Difficulty of detecting and measuring
If internal signals are extracted using traditional methods, then debugging can be performed, but bus traffic increases and memory resources are overwhelmed
Solution Approach 1:
The embedded logic analyzer extracts only the specific internal logic signals that are relevant for debugging, rather than extracting all internal signals. The comparison blocks selectively capture signals based on predetermined conditions, and the buffer memory stores only the captured debug data, thereby minimizing bus traffic and memory resource consumption
Solution Approach 2:
The logic analyzer performs preliminary signal capture and filtering within the chip before transferring data externally. The comparison blocks pre-process internal signals by comparing them against reference values and capturing only meaningful events, reducing the volume of data that needs to be transmitted over the bus and stored in memory
Data Source
AI summary
An embedded logic analyzer of an integrated circuit includes a comparison block configured to generate a capture data signal and a plurality of comparison enable signals based on an input data signal from one of function blocks included in the integrated circuit such that the comparison enable signals are activated respectively based on different comparison conditions; an operation block configured to perform a logic operation on the comparison enable signals to generate a data enable signal indicating a data capture timing; and packer circuitry configured to generate a packer data signal including capture data and capture time information based on the capture data signal, the data enable signal and a time information signal.