Embedded LSI Package Substrate Layout for Low-Warpage Multi-Die Integration

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Solution Overview

Problem

The increasing complexity and size of integrated circuits lead to warpage issues and reduced manufacturing yield in packaging processes, particularly when multiple device dies are interconnected.

Innovation Solution

The integration of a Local Silicon Interconnect (LSI) die within an Integrated Fan-Out (InFO) package substrate, which is built layer-by-layer and extends beyond the edges of underlying device dies, reducing warpage and improving yield by embedding discrete components directly to the InFO package substrate, rather than using Chip-on-Wafer-on-Substrate packages.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If multiple device dies are interconnected to integrate more functions, then functionality is improved, but warpage increases

Engineering Contradiction:

ImprovefunctionalityVSAvoidwarpage

Core Design Contradiction:

Adaptability or versatilityVSStability of the object's composition

Solution Approach 1:

The LSI die is embedded within the InFO package substrate, creating a nested structure where one component is integrated inside another. This nesting approach allows multiple device dies to be interconnected on a compact substrate while maintaining structural stability and reducing warpage compared to traditional multi-die packaging.

Inventive Principle:

Principle #7Nested doll (Nesting)

Solution Approach 2:

The patent transitions from traditional planar multi-die packaging to a three-dimensional embedded structure where the LSI die is integrated within the substrate layers. This dimensional change enables better stress distribution and reduced warpage while achieving high functionality integration.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Adaptability or versatility

If package size and complexity increase to integrate more functions, then functionality is improved, but manufacturing yield decreases

Engineering Contradiction:

ImprovefunctionalityVSAvoidmanufacturing yield

Core Design Contradiction:

Adaptability or versatilityVSProductivity

Solution Approach 1:

The LSI die and InFO package substrate are merged into a single integrated structure through embedding. This combination simplifies the manufacturing process by reducing the number of separate components and assembly steps, thereby improving manufacturing yield while achieving high functionality integration.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The LSI die is embedded within the InFO package substrate during the substrate fabrication process itself, rather than adding it later. This preliminary action integrates multiple functions early in manufacturing, simplifying subsequent steps and improving overall manufacturing yield.

Inventive Principle:

Principle #10Preliminary action

3Reliability

If Chip-on-Wafer-on-Substrate packages are used to interconnect device dies, then electrical connectivity is improved, but warpage increases

Engineering Contradiction:

Improveelectrical connectivityVSAvoidwarpage

Core Design Contradiction:

ReliabilityVSStability of the object's composition

Solution Approach 1:

Instead of stacking separate wafer and substrate layers that cause warpage, the LSI die is nested within the InFO package substrate layers. This embedded structure maintains excellent electrical connectivity while distributing mechanical stress uniformly, thereby reducing warpage.

Inventive Principle:

Principle #7Nested doll (Nesting)

4Reliability

If discrete components are connected through intermediate packages, then electrical connectivity is achieved, but insertion loss increases

Engineering Contradiction:

Improveelectrical connectivityVSAvoidinsertion loss

Core Design Contradiction:

ReliabilityVSLoss of energy

Solution Approach 1:

The LSI die and InFO package substrate are merged into a tightly integrated structure with direct electrical connections. This eliminates intermediate packaging interfaces that cause signal reflection and insertion loss, achieving low-loss electrical connectivity.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

Electrical interconnections are established during the substrate fabrication process itself, before final assembly. This preliminary connection approach minimizes the number of bonding interfaces and reduces insertion loss compared to traditional multi-step packaging processes.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS20250349732A1Semiconductor package and method of forming the same

Publication Date: 2025.11.13 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A method includes forming a composite package substrate. The formation of the composite package substrate includes encapsulating an interconnect die in an encapsulant, with the interconnect die including a plurality of through-vias therein, and forming a first plurality of redistribution lines (RDLs) and a second plurality of RDLs on opposite sides of the interconnect die. The method further includes bonding an organic package substrate to the composite package substrate, and bonding a first package component and a second package component to the first plurality of RDLs. The first package component and the second package component are electrically interconnected through the interconnect die and the first plurality of RDLs.