Embedded LSI and TSV Package Structure for Dense Die-to-Die Interconnects
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Solution Overview
Problem
The semiconductor industry faces challenges in achieving higher integration density, faster speeds, lower power consumption, and reduced latency due to limitations in packaging techniques and interconnect structures, particularly in miniaturizing semiconductor devices and enhancing connectivity between semiconductor dies.
Innovation Solution
The development of advanced interconnect structures and packaging methods, including the formation of high-density redistribution layers with fine-pitch connections and the use of polymer layers, conductive materials, and encapsulants, along with the integration of local interconnect devices and through-substrate vias, to facilitate efficient die-to-die communication and reduce silicon current leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If minimum feature size is reduced to increase integration density, then more components can be integrated into a given area, but manufacturing precision and reliability become more difficult to maintain
Solution Approach 1:
The patent transitions from planar 2D integration to 3D vertical stacking architecture, where multiple semiconductor dies are stacked and interconnected through through-silicon vias (TSVs). This dimensional change allows integration density to increase volumetrically rather than areally, enabling more components to be integrated without continuously shrinking feature sizes, thus maintaining manufacturing precision while achieving higher integration density.
Solution Approach 2:
The patent implements a nested structure where multiple functional layers are stacked vertically, with each layer containing interconnect structures, active devices, and passive devices embedded within dielectric materials. The through-silicon vias penetrate through multiple die layers, creating a nested configuration where conductive interconnects are embedded within insulating materials, which are in turn stacked with active and passive devices, achieving high integration without continuous miniaturization.
2Area of moving object
If packaging techniques are miniaturized to reduce device footprint, then smaller form factors are achieved, but structural integrity and reliability may be compromised
Solution Approach 1:
The patent moves from 2D lateral expansion to 3D vertical stacking, reducing the device footprint by stacking multiple functional layers vertically. The structural integrity is maintained through robust through-silicon via structures that provide mechanical support and electrical interconnection between stacked dies, and through the use of reinforced interconnect structures that can withstand thermal and mechanical stresses in the compact 3D configuration.
Solution Approach 2:
The patent employs composite material structures combining multiple materials with complementary properties: conductive materials (copper, tungsten) for interconnects, dielectric materials (silicon dioxide, silicon nitride) for insulation and mechanical support, and barrier materials for stress control. These composite structures provide both the miniaturization needed for small footprint and the structural integrity required for reliability in the compact package.
3Productivity
If interconnect density is increased to enhance die-to-die connectivity, then bandwidth and speed are improved, but silicon current leakage increases
Solution Approach 1:
The patent applies different material properties to different regions of the interconnect structure: conductive materials are used specifically in the interconnect pathways where current flow is desired, while dielectric materials with appropriate breakdown voltages are used in regions where electrical isolation is needed. Barrier and adhesion layers are selectively applied at material interfaces to prevent diffusion and control electrical properties locally, thereby enabling high interconnect density while minimizing current leakage through precise local material selection and configuration.
Data Source
AI summary
Interconnect devices, packaged semiconductor devices and methods are disclosed herein that are directed towards embedding a local silicon interconnect (LSI) device and through substrate vias (TSVs) into system on integrated substrate (SoIS) technology with a compact package structure. The LSI device may be embedded into SoIS technology with through substrate via integration to provide die-to-die FL connection arrangement for super large integrated Fan-Out (InFO) for SBT technology in a SoIS device. Furthermore, the TSV connection layer may be formed using lithographic or photoresist-defined vias to provide eLSI P/G out to a ball-grid-array (BGA) connection interface.