Embedded Package Magnetic-Core Coil for Low-Resistance IVR Inductors
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Solution Overview
Problem
The challenge in microprocessor packages is the increasing dc resistance of copper traces in air-core inductors due to reduced z-height constraints, leading to a decrease in the quality factor of inductors and overall efficiency of integrated voltage regulators (IVRs).
Innovation Solution
The integration of multi-turn inductors within a magnetic core embedded in the package substrate, where the inductor windings are formed as conductor traces within the substrate's dielectric layers, maintaining a low z-height and high inductance density, and are interconnected to minimize negative magnetic coupling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If air-core inductors are used with reduced z-height constraints, then package footprint is reduced, but dc resistance of copper traces increases leading to decreased quality factor
Solution Approach 1:
The patent employs a magnetic core composite structure that combines magnetic material with copper trace windings embedded within the package substrate. This composite approach concentrates magnetic flux within the magnetic core material, enabling higher inductance density in a smaller footprint while the magnetic core reduces flux leakage and improves efficiency, thereby addressing both the footprint reduction and energy loss concerns
Solution Approach 2:
The patent changes the fundamental parameters of the inductor design by transitioning from air-core to magnetic core, and from discrete components to embedded conductor traces within the substrate. This parameter change enables higher inductance per unit area and reduced dc resistance by optimizing the magnetic path and conductor geometry within the package, directly resolving the contradiction between footprint and energy loss
2Manufacturing precision
If copper trace thickness is limited to 25 microns or less, then manufacturing precision is maintained, but quality factor of inductors decreases due to increased resistive losses
Solution Approach 1:
The patent moves the inductor windings from the traditional planar surface layer to embedded layers within the package substrate's dielectric structure. This dimensional transition allows for optimized trace routing through multiple layers, reducing the required trace length and resistance while maintaining manufacturing precision, thereby improving quality factor without sacrificing fabrication control
Solution Approach 2:
The patent embeds the copper trace windings within the substrate's dielectric layers, nesting the conductor traces inside the package structure rather than placing them on the surface. This nesting approach allows for optimized current paths, reduced resistance, and improved quality factor while maintaining compatibility with standard manufacturing processes and precision control
3Quantity of substance
If multi-turn inductors are embedded in magnetic core, then inductance density increases, but device complexity increases
Solution Approach 1:
The patent merges the inductor windings with the package substrate structure by embedding the conductor traces directly within the substrate's dielectric layers. This integration combines multiple functions (substrate support, electrical interconnection, and inductor formation) into a single unified structure, achieving high inductance density without proportionally increasing device complexity
Solution Approach 2:
The package substrate serves multiple functions simultaneously: it provides mechanical support, electrical interconnection, and hosts the embedded multi-turn inductors within its dielectric layers. This multi-functionality approach achieves high inductance density while avoiding additional complexity by making the substrate itself the inductor carrier rather than requiring separate inductor components
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the inductance density and efficiency of IVRs while maintaining a compact package footprint, reducing reactive latency and improving performance and battery life.
Implementation Method 1
multi-turn inductors within a magnetic core embedded in the package substrate
Implementation Method 2
inductor windings are formed as conductor traces within the substrate's dielectric layers
Data Source
AI summary
A microelectronics package comprising a substrate, the substrate comprising a dielectric and at least first and second conductor level within the dielectric, where the first and second conductor levels are separated by at least one dielectric layer. The microelectronics package comprises an inductor structure that comprises a magnetic core. The magnetic core is at least partially embedded within the dielectric. The inductor structure comprises a first trace in the first conductor level, a second trace in the second conductor level, and a via interconnect connecting the first and second traces. The first trace and the second trace extend at least partially within the magnetic core.