Embedded Magnetic Inductor Structure for Low-Profile SMPS Packaging
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Solution Overview
Problem
Existing semiconductor packaging solutions with discrete inductors are limited by thickness, design flexibility, and cost, particularly for high input voltage and low switching frequency applications, and require substantial volumes for production, making them unsuitable for advanced semiconductor devices like CPUs.
Innovation Solution
The development of semiconductor devices with embedded magnetic inductors that include a magnetic layer, dielectric layer, substrate layer, and plated-through hole vias, allowing for the creation of multi-turn higher valued magnetic inductors with low DC resistance, enabling operation at higher input voltages and lower switching frequencies while maintaining a low z-height and enabling custom inductor designs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If discrete inductors are used with semiconductor packages, then voltage regulation is achieved, but the z-height increases and design flexibility is limited
Solution Approach 1:
The patent combines the discrete inductor with the semiconductor package substrate to form an integrated structure. The inductor is embedded within the package substrate layers, merging two previously separate components into a unified assembly, thereby reducing overall z-height while maintaining voltage regulation functionality
Solution Approach 2:
The inductor structure is nested within the package substrate layers. The substrate layers are configured to surround and embed the inductor, creating a nested configuration where the inductor is contained within the substrate structure, reducing the overall height profile
2Length of moving object
If discrete inductors are embedded in package core, then z-height is reduced, but core thickness must be 700 μm or thicker which is not suitable for CPU parts
Solution Approach 1:
The package substrate is segmented into multiple thinner layers rather than requiring a single thick core. The substrate layers are configured to surround the inductor in a distributed manner across multiple layers, eliminating the need for a single thick core while achieving the same electromagnetic shielding and structural support functions
Solution Approach 2:
The solution transitions from a single-thick-core approach to a multi-layer distributed configuration. By distributing the substrate layers around the inductor in a vertical stacking arrangement, the patent achieves equivalent functionality with reduced individual layer thicknesses, making it suitable for CPU packaging
3Adaptability or versatility
If multi-turn inductors are created with plated-through hole vias, then inductance value increases, but manufacturing complexity increases
Solution Approach 1:
The plated-through hole vias serve multiple functions: they provide mechanical support, electrical connectivity between layers, and form the conductive windings of the inductor. This multi-functionality reduces the need for separate manufacturing steps and simplifies the overall manufacturing process while achieving high inductance values
Solution Approach 2:
The patent adjusts manufacturing parameters such as via diameter, copper plating thickness, and winding turn count to optimize inductance values. By controlling these parameters during standard PCB manufacturing processes, the patent achieves a range of inductance values without requiring specialized or complex manufacturing equipment
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution provides semiconductor devices capable of efficient voltage conversion across a wide range of frequencies and voltages with reduced z-height, lower production costs, and increased design flexibility, suitable for advanced semiconductor applications.
Implementation Method 1
Package embedded magnetic inductor structures and manufacturing techniques for 5-50 mhz SMPS operations
Implementation Method 2
a plurality of PTH vias in the dielectric layer and the substrate layer, wherein the plurality of PTH vias vertically extend from the first conductive layer to the second conductive layer
Data Source
AI summary
Embodiments include inductors and methods to form the inductors. An inductor includes a substrate layer that surrounds a magnetic layer, where the magnetic layer is embedded between the substrate layer. The inductor also includes a dielectric layer that surrounds the substrate and magnetic layers, where the dielectric layer fully embeds the substrate and magnetic layers. The inductor further includes a first conductive layer over the dielectric layer, a second conductive layer below the dielectric layer, and a plurality of plated-through-hole (PTH) vias in the dielectric and substrate layers. The PTH vias vertically extend from the first conductive layer to the second conductive layer, and the magnetic layer in between the PTH vias. The magnetic layer may have a thickness that is substantially equal to a thickness of the substrate layer, where the thickness of the magnetic layer is less than a thickness defined between the first and second conductive layers.