Embedded Planar Magnetic Inductors for Disaggregated VR Paths
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Solution Overview
Problem
Current voltage regulator (VR) circuitry is co-located with processing cores, leading to increased manufacturing costs and complexity due to the use of advanced processing nodes, and moving VR circuitry off the processing core results in decreased performance due to difficulty in providing a low impedance path.
Innovation Solution
Implementing planar magnetic radial inductors that are embedded in the package substrate, allowing VR circuitry to be disaggregated from the processing core, with the inductors spanning between VR circuitry and load dies, and utilizing magnetic material to control inductance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If VR circuitry is co-located with processing cores on advanced processing nodes, then power regulation proximity to load is improved, but manufacturing cost and device complexity increase
Solution Approach 1:
The patent segments the VR circuitry from the processing core, placing the VR circuitry on a separate package substrate rather than integrating it into the processing core die. This segmentation allows each component to be optimized independently for its specific function while maintaining electrical connection through the package substrate.
Solution Approach 2:
The patent introduces an intermediary package substrate that houses the VR circuitry and provides electrical connection between the VR circuitry and the processing core load. This intermediary structure resolves the contradiction by providing proximity for power regulation while avoiding direct integration into the advanced node processing core.
2Ease of manufacture
If VR circuitry is disaggregated from processing cores to improve manufacturing efficiency, then manufacturing cost and complexity are reduced, but performance decreases due to increased impedance path
Solution Approach 1:
The patent changes the physical parameters of the connection path by implementing controlled impedance traces and low-inductance vias in the package substrate. These parameter optimizations ensure that the disaggregated VR circuitry maintains low impedance paths for power delivery, preserving performance while enabling manufacturing benefits.
Solution Approach 2:
The patent applies local quality optimization by designing specific low-impedance connection paths in the package substrate between the VR circuitry and the processing core. The package substrate is engineered with specialized trace geometries and via structures in the critical power delivery regions to minimize impedance while other areas can use standard packaging materials and processes.
3Reliability
If complex analog VR circuitry is added to processing core, then power regulation capability is improved, but porting difficulty between process nodes increases
Solution Approach 1:
The patent segments the analog VR circuitry from the digital processing core, placing the voltage-regulating components on a separate package substrate. This allows the processing core to remain as a pure digital logic device that can be freely ported between process nodes, while the VR circuitry remains stationary on the package substrate.
Solution Approach 2:
The patent extracts the complex analog VR circuitry from the processing core die and relocates it to the package substrate. This extraction removes the portability barrier, allowing the processing core to be manufactured on different process nodes without being constrained by the presence of analog power regulation circuitry.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Reduces manufacturing costs and simplifies porting between process nodes while maintaining performance by providing a low impedance path for VR circuitry.
Implementation Method 1
a magnetic material surrounding the trace between the first end and the second end
Data Source
AI summary
Embodiments disclosed herein include electronic packages with embedded inductors. In an embodiment, an electronic package comprises a package substrate, where the package substrate comprises a plurality of dielectric layers. In an embodiment, the electronic package further comprises an inductor embedded in the package substrate, where the inductor comprises: a trace with a first end and a second end. In an embodiment, a magnetic material surrounds the trace between the first end and the second end. In an embodiment, a first via is connected to the first end, and a second via is connected to the second end.