Embedded Memory Anti-Dishing Structure for CMP Edge Uniformity
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Solution Overview
Problem
In integrated circuit manufacturing, the 'dishing' effect during the chemical mechanical polishing (CMP) process can lead to shortened gate electrodes at the edges of memory arrays, causing threshold voltage variations and nickel contamination, which can result in partial or complete failure of memory devices.
Innovation Solution
The implementation of a dummy hardmask and/or dummy select gate electrode structure on the isolation structure provides additional structural rigidity, ensuring planarized and equal height top surfaces for gate electrodes, thereby mitigating the 'dishing' effect and reducing threshold voltage variations and nickel contamination.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If gate electrodes are shortened due to dishing, then manufacturing simplicity is maintained, but threshold voltage variations and nickel contamination occur causing device failure
Solution Approach 1:
The patent implements preliminary action by forming the boundary structure with nitride layers and sidewall spacers before the CMP process and subsequent manufacturing steps. This pre-established structural framework prevents gate electrode shortening and the associated threshold voltage variations and nickel contamination from occurring in the first place, thereby maintaining both manufacturing simplicity and device reliability without requiring additional corrective steps.
Data Source
AI summary
Some embodiments of the present application are directed towards an integrated circuit (IC). The integrated circuit includes a semiconductor substrate having a peripheral region and a memory cell region separated by an isolation structure. The isolation structure extends into a top surface of the semiconductor substrate and comprises dielectric material. A logic device is arranged on the peripheral region. A memory device is arranged on the memory region. The memory device includes a gate electrode and a memory hardmask over the gate electrode. An anti-dishing structure is disposed on the isolation structure. An upper surface of the anti-dishing structure and an upper surface of the memory hardmask have equal heights as measured from the top surface of the semiconductor substrate.