Embedded Memory Channel Stop Implants for Leakage Reduction
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Solution Overview
Problem
The formation of NMOS and PMOS transistors in integrated circuits using shared ion implant steps and photolithographic processes compromises logic circuit speed due to increased junction capacitance and memory cell leakage current, while dedicated channel stop implants for separate transistors increase fabrication costs.
Innovation Solution
Implementing a global mask to implant dopants for both logic and memory transistors, followed by a memory mask to selectively implant additional dopants for memory transistors, allowing for varying dopant densities to optimize channel stop layers and reduce leakage current and capacitance, thereby reducing fabrication costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the same ion implant dose is used for both logic and memory transistors, then fabrication costs are reduced, but logic circuit speed decreases due to increased junction capacitance
Solution Approach 1:
The patent applies different dopant densities to different regions: a first dopant density for logic transistors and a second dopant density for memory transistors. This allows optimization of each region's performance characteristics - lower dose for logic to reduce capacitance and higher dose for memory to reduce leakage - while using a unified process approach that maintains manufacturing efficiency.
2Ease of manufacture
If the same ion implant dose is used for both logic and memory transistors, then fabrication costs are reduced, but memory cell leakage current increases
Solution Approach 1:
The patent implements spatially varying dopant densities where memory transistor regions receive a higher dopant density than logic transistor regions. This localized differentiation specifically addresses memory leakage issues by increasing the channel stop doping in memory regions while maintaining logic region performance through lower doping.
3Reliability
If dedicated implant operations are used for separate channel stops in logic and memory cells, then logic speed and memory leakage are optimized, but fabrication costs increase due to additional photolithographic steps
Solution Approach 1:
The patent employs a single photolithographic mask pattern that simultaneously defines both logic and memory transistor regions. This universal masking approach enables differentiated dopant implantation for the two transistor types without requiring separate photolithographic steps, thereby achieving performance optimization while maintaining manufacturing efficiency.
Solution Approach 2:
The patent varies the dopant density parameter between logic and memory regions while using the same photolithographic mask. By changing only the implantation parameters (dopant density, energy, or duration) rather than the mask pattern itself, the process achieves differentiated doping profiles without additional lithographic complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances logic circuit speed by reducing drain capacitance and memory cell leakage current while minimizing additional photolithographic steps, thus lowering fabrication costs and improving integrated circuit efficiency.
Implementation Method 1
A global channel stop dose of dopants of a same polarity as the logic and memory channel stop layers is implanted into the substrate in the logic and memory MOS transistors
Data Source
AI summary
An integrated circuit contains a logic MOS transistor and a memory MOS transistor of a same polarity. The logic MOS transistor has a logic channel stop layer. The memory MOS transistor has a memory channel stop layer. An average dopant density of the memory channel stop layer is higher than an average dopant density of the logic channel stop layer. The integrated circuit is formed by forming a global mask which exposes both the logic and memory MOS transistors. A global channel stop dose of dopants is implanted in the logic and memory MOS transistors. A memory mask is formed which exposes the memory MOS transistor and covers the logic MOS transistor. A memory channel stop dose of dopants of the same polarity is implanted into the memory MOS transistors. The memory channel stop dose of dopants is blocked from the logic MOS transistors.