Embedded Memory in CMOS Circuits Using Two-Terminal Elements
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Solution Overview
Problem
There is a need for cost-effective embedded non-volatile memory solutions that can be integrated with existing CMOS fabrication processes, particularly for applications requiring small amounts of memory in circuits like ASICs, where existing options are inefficient in terms of memory density and substrate usage.
Innovation Solution
The integration of two-terminal memory elements, such as diode-based memory devices, within CMOS circuits, where the two-terminal memory elements are formed between a gate layer and a metal layer, utilizing CMOS transistors to program these elements, allowing for increased memory density and efficient use of substrate space with minimal disruption to existing fabrication processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If traditional non-volatile memory options (floating gate memory devices, diode-based memory devices) are used, then memory functionality is achieved, but manufacturing cost increases and integration with existing CMOS fabrication processes becomes difficult
Solution Approach 1:
The patent merges the formation of two-terminal memory elements with the existing CMOS transistor fabrication process by using the same gate layer (polysilicon layer) for both the CMOS transistor gate electrode and the memory element electrode. This integration allows memory structures to be formed alongside logic circuits in the same fabrication sequence, eliminating the need for separate memory fabrication processes and reducing manufacturing complexity while maintaining reliable memory functionality.
Solution Approach 2:
The gate layer deposited during CMOS transistor fabrication serves dual purposes: forming the gate electrode for CMOS transistors and simultaneously forming one electrode of the two-terminal memory elements. This multi-functional use of the polysilicon gate layer enables both logic and memory functions to be integrated on the same substrate using a single fabrication process, improving ease of manufacture while ensuring reliable operation of both transistor and memory functions.
2Area of stationary object
If memory density is increased to reduce substrate space usage, then area efficiency improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent transitions from planar memory structures to vertically-oriented two-terminal memory elements that extend between metal interconnect layers. By utilizing the vertical dimension between conductive layers rather than only horizontal substrate space, the design achieves high memory density without requiring proportionally higher manufacturing precision, as the vertical structure leverages existing layer thicknesses and spacing already controlled in standard CMOS fabrication.
Solution Approach 2:
The memory array is segmented into multiple two-terminal memory elements distributed across different locations on the substrate, with each element formed using the same standardized process steps. This segmentation allows the memory function to be distributed throughout the substrate area, improving overall area efficiency while maintaining consistent, achievable manufacturing precision requirements for each individual memory element through repeated use of established fabrication processes.
Data Source
AI summary
In some aspects, a memory circuit is provided that includes (1) a two-terminal memory element formed on a substrate; and (2) a CMOS transistor formed on the substrate and adapted to program the two-terminal memory element. The two-terminal memory element is formed between a gate layer and a first metal layer of the memory circuit. Numerous other aspects are provided.