Embedded Memory Layout for Wider Dielectric Fill Windows
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Solution Overview
Problem
The formation of sidewall spacers in integrated circuit manufacturing narrows the lateral spaces between adjacent select gate electrodes, leading to high aspect ratios and potential voids in inter-layer dielectric material, causing defects such as unwanted shorting or bridging during subsequent processes.
Innovation Solution
The integrated circuit design omits sidewall spacers on memory cell structures, allowing the contact etch stop layer to directly contact the logic region's sidewall spacer, thereby enlarging the inter-layer dielectric fill spaces and reducing void formation by ensuring better filling of the inter-layer dielectric between adjacent memory cell structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If sidewall spacers are formed in memory region, then select gate electrode separation is improved, but inter-layer dielectric fill space is reduced causing high aspect ratios and voids
Solution Approach 1:
The patent applies local quality by differentiating the treatment between memory region and logic region. Sidewall spacers are formed only in the logic region to provide electrode separation where needed, while the memory region maintains larger fill spaces for proper inter-layer dielectric filling. This regional differentiation resolves the contradiction by allowing selective spacer formation that satisfies both separation and filling requirements in different areas.
2Manufacturing precision
If sidewall spacers are formed, then device structure definition is improved, but lateral space between electrodes is reduced leading to high aspect ratios
Solution Approach 1:
The patent segments the semiconductor device into distinct memory region and logic region with different structural characteristics. The sidewall spacers are selectively formed only in the logic region, creating a segmented approach where each region has optimized structure for its specific function. This segmentation allows the logic region to have well-defined structures with spacers while the memory region maintains larger lateral spaces.
3Manufacturing precision
If inter-layer dielectric fill space is reduced, then electrode separation is improved, but void formation increases causing shorting and bridging defects
Solution Approach 1:
The patent introduces a regional distinction as an intermediary concept to mediate between the conflicting requirements of electrode separation and void prevention. By defining separate memory and logic regions with different spacer configurations, the patent creates an intermediate structure that allows both tight separation where needed (logic region) and adequate fill space where required (memory region), thereby preventing void formation and associated defects.
Data Source
AI summary
Various embodiments of the present application are directed to an IC, and associated forming methods. In some embodiments, the IC comprises a memory region and a logic region integrated in a substrate. A plurality of memory cell structures is disposed on the memory region. Each memory cell structure of the plurality of memory cell structures comprises a control gate electrode disposed over the substrate, a select gate electrode disposed on one side of the control gate electrode, and a spacer between the control gate electrode and the select gate electrode. A contact etch stop layer (CESL) is disposed along an upper surface of the substrate, extending upwardly along and in direct contact with a sidewall surface of the select gate electrode within the memory region. A lower inter-layer dielectric layer is disposed on the CESL between the plurality of memory cell structures within the memory region.