Embedded Memory Semiconductor Chip Using 3D FinFET Integration
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Solution Overview
Problem
The semiconductor industry faces challenges in achieving higher integration density, lower power consumption, and faster speeds due to limitations in miniaturization and bandwidth, particularly in the development of semiconductor chips with embedded memory cells.
Innovation Solution
The development of a FinFET structure with fins patterned using photolithography and self-aligned processes, combined with advanced materials and processes such as epitaxial growth, gate replacement, and interconnect formation, to create a semiconductor chip with integrated memory devices and transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If minimum feature size is reduced to increase integration density, then more components can be integrated into a given area, but manufacturing precision and process control become more difficult
Solution Approach 1:
The patent transitions from planar 2D transistor layouts to 3D FinFET structures with vertical fins extending from the substrate. This dimensional change allows integration density to increase through vertical scaling rather than further lateral miniaturization, thereby avoiding the manufacturing precision challenges associated with reducing minimum feature size while still achieving higher component density.
2Quantity of substance
If continuous miniaturization is pursued to increase integration density, then more components fit in given area, but device complexity and process fabrication difficulty increase
Solution Approach 1:
The fabrication process is divided into distinct modular stages: forming sacrificial mandrels, depositing conformal spacer layers, selectively removing mandrels, and forming fins. This segmentation of the complex fabrication process into manageable steps reduces overall process complexity while enabling the creation of three-dimensional FinFET structures that achieve higher integration density.
3Ease of manufacture
If traditional planar transistor structures are used, then manufacturing is simpler, but integration density and bandwidth are limited
Solution Approach 1:
The FinFET structure embeds vertical fins within a planar substrate architecture, nesting three-dimensional features inside the traditional two-dimensional device layout. This nesting approach maintains compatibility with conventional planar manufacturing processes while achieving higher integration density through the vertical fin structures that extend upward from the substrate plane.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the fabrication of semiconductor chips with increased integration density, reduced power consumption, and improved performance by allowing for more efficient integration of memory cells and transistors, enhancing both speed and bandwidth.
Implementation Method 1
fins patterned using photolithography
Implementation Method 2
epitaxial growth
Data Source
AI summary
A semiconductor chip including a semiconductor substrate, an interconnect structure and a memory cell array is provided. The semiconductor substrate includes a logic circuit. The interconnect structure is disposed on the semiconductor substrate and electrically connected to the logic circuit, and the interconnect structure includes stacked interlayer dielectric layers and interconnect wirings embedded in the stacked interlayer dielectric layers. The memory cell array is embedded in the stacked interlayer dielectric layers. The memory cell array includes driving transistors and memory devices, and the memory devices are electrically connected the driving transistors through the interconnect wirings.