Embedded Memory HV Trench Transistor for Height Uniformity
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Solution Overview
Problem
Integrated circuit (IC) manufacturing faces challenges with device height uniformity and planarization issues due to enlarged device areas and thicker gate dielectrics in high voltage devices, leading to metal layer loss, sheet resistance, and threshold voltage variations.
Innovation Solution
The implementation of a trench gate high voltage transistor structure where the logic gate dielectric and electrode are positioned within a trench in the substrate, reducing lateral device area and protecting the top surface from planarization damage, thereby improving uniformity and reducing manufacturing issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high voltage devices use larger dimensions and thicker gate dielectric, then they can bear high operating voltage level, but device height uniformity deteriorates and planarization issues occur
Solution Approach 1:
The patent transitions from planar gate structures to three-dimensional trench gate structures. The gate electrode is positioned within a trench etched into the substrate, allowing the gate dielectric to wrap around the gate electrode on multiple surfaces. This dimensional change enables thicker gate dielectric for high voltage operation while maintaining compact lateral footprint and improving device height uniformity through the trench configuration.
Solution Approach 2:
The gate electrode is nested within the trench structure, with the gate dielectric surrounding the gate electrode. This nested configuration allows the gate dielectric to provide enhanced insulation and voltage handling capability while the entire structure fits within a compact lateral space, resolving the conflict between thickness requirements and uniformity requirements.
2Reliability
If high voltage devices use larger dimensions, then they can operate at high voltage level, but lateral device area increases causing poor device height uniformity
Solution Approach 1:
By moving the gate structure into a vertical trench configuration, the patent utilizes the vertical dimension to accommodate the gate electrode and dielectric. This eliminates the need for larger lateral dimensions while maintaining high voltage capability, as the voltage handling is achieved through the trench depth and dielectric thickness rather than lateral expansion.
Solution Approach 2:
The trench gate structure concentrates the high voltage handling capability in the local region of the trench, where the gate dielectric provides enhanced insulation. The surrounding circuitry can use standard planar structures, optimizing each region for its specific function while maintaining overall compactness.
3Manufacturing precision
If planarization process is applied to devices with different heights, then surface uniformity is improved, but metal layer loss occurs due to gate metal removal
Solution Approach 1:
The trench gate structure positions the gate electrode below the substrate surface level. This allows the planarization process to fill and flatten the trench region without removing the gate metal, as the gate is protected within the trench structure. The planarization can proceed uniformly across the surface without causing metal layer loss.
Data Source
AI summary
Various embodiments of the present application are directed to an IC, and associated forming methods. In some embodiments, the IC has a plurality of logic devices disposed on a logic region of a substrate, including a first logic device configured to operate at a first voltage and comprising a first logic gate electrode separated from the substrate by a first logic gate dielectric. The first logic gate dielectric is disposed along sidewall and bottom surfaces of a logic device trench of the substrate, and the first logic gate electrode is disposed conformally along the first logic gate dielectric within the logic device trench. A hard mask layer is disposed on the first logic gate electrode within the logic device trench.