Embedded Memory Arrays in Metal Wiring Layers
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Solution Overview
Problem
Current semiconductor technologies face challenges in integrating high-density memory cells within metal wiring layers, particularly in efficiently utilizing space for both memory arrays and logic circuitry, leading to inefficiencies in chip design and increased costs.
Innovation Solution
The integration of memory arrays in lower metal wiring layers, such as the third and fourth layers, with stacked metal layers, selector layers, and memory layers, along with peripheral circuits below the memory arrays, allows for a high-density configuration that optimizes space usage and facilitates easier integration with logic circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If memory cells are integrated in metal wiring layers, then chip area consumption is reduced and integration is improved, but manufacturing complexity increases
Solution Approach 1:
The patent integrates memory cells within existing metal wiring layers (M3, M4, etc.) by utilizing the vertical stacking dimension and interlayer dielectric spaces, rather than adding separate memory structures. This allows memory functionality to be embedded in the BEOL without increasing lateral chip area, while using the third dimension (vertical stacking) to accommodate multiple memory layers and wiring levels simultaneously.
Solution Approach 2:
The metal wiring layers serve dual purposes: they function as both interconnect wiring for logic circuits and as bit lines for memory arrays. The same metal layers and via structures are reused for both logic and memory functionality, eliminating the need for separate dedicated memory wiring and reducing overall manufacturing steps.
2Productivity
If high-density memory arrays are embedded in metal layers, then integration efficiency is improved, but design flexibility is constrained
Solution Approach 1:
The patent divides the chip into distinct logic regions and memory regions, with memory arrays embedded in specific metal layers (M3, M4) while logic circuits occupy other areas. This segmentation allows independent optimization of logic and memory portions, enabling flexible placement and routing decisions without compromising overall integration efficiency.
Solution Approach 2:
The design allows dynamic configuration where memory arrays can be selectively formed in different metal layers depending on design requirements. The embedded memory structure supports variable density and can be adapted to different process nodes and application needs, maintaining design flexibility while achieving high integration.
3Area of stationary object
If peripheral circuits are placed below memory arrays, then space utilization is optimized, but manufacturing precision requirements increase
Solution Approach 1:
The patent forms peripheral circuits in lower metal layers (M1, M2) before embedding memory arrays in upper metal layers (M3, M4). This preliminary placement of peripheral circuits establishes a foundation that guides subsequent memory formation, allowing better control over alignment and reducing precision requirements for later steps.
Solution Approach 2:
The structure implements a nested arrangement where peripheral circuits are embedded within the space below memory arrays, similar to nested dolls. This vertical nesting optimizes two-dimensional space utilization by using the vertical dimension to separate different functional blocks, reducing the need for precise lateral alignment while maintaining compact integration.
Data Source
AI summary
A semiconductor device includes logic circuitry including a transistor disposed over a substrate, multiple layers each including metal wiring layers and an interlayer dielectric layer, respectively, disposed over the logic circuitry, and memory arrays. The multiple layers of metal wiring include, in order closer to the substrate, first, second, third and fourth layers, and the memory arrays include lower multiple layers disposed in the third layer.