Embedded Memory Logic Layout With Multi-Recess Voltage Regions
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Solution Overview
Problem
The integration of logic devices with different voltage levels in embedded memory ICs faces challenges such as gate dielectric thickness limitations and pattern density issues during chemical mechanical polishing (CMP) processes, leading to dishing or erosion, which affects the process window and device performance.
Innovation Solution
The solution involves forming logic devices on multiple recessed positions of a substrate, allowing for improved design flexibility and suitable operation at various voltage levels by varying the gate dielectric thickness and lateral dimensions, and positioning devices to mitigate CMP-related issues through strategic recessing processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If logic devices are integrated with different voltage levels on the same chip, then functional density and versatility are improved, but gate dielectric thickness control and manufacturing precision deteriorate due to CMP process limitations
Solution Approach 1:
The patent applies local quality by creating different recess depths in different logic regions. High voltage logic devices are formed in first recesses with greater depth, while low voltage logic devices are formed in second recesses with lesser depth. This allows each region to have optimized gate dielectric thickness tailored to its specific voltage requirements, resolving the contradiction between multi-voltage versatility and manufacturing precision.
Solution Approach 2:
The patent introduces a vertical dimension by forming recesses at different depths in the substrate. Instead of varying gate dielectric thickness in a single plane, the solution moves to three-dimensional space by creating multiple recess levels. This dimensional change enables different effective gate dielectric thicknesses for different voltage devices while maintaining uniform actual dielectric deposition, thus resolving the manufacturing precision issue.
2Reliability
If gate dielectric thickness is varied for different voltage levels, then device performance is improved, but pattern density control and CMP process window deteriorate
Solution Approach 1:
The patent segments the substrate into multiple recess regions with different depths. By dividing the chip into distinct high voltage and low voltage logic regions with separate recesses, the pattern density can be independently controlled in each segment. This segmentation allows optimization of device performance for each voltage level while simplifying CMP process control within each uniform-density region.
3Adaptability or versatility
If multiple logic devices with different voltages are integrated, then embedded memory functionality is improved, but process window and manufacturing yield deteriorate due to CMP dishing and erosion
Solution Approach 1:
By creating local recesses with specific depths in different logic regions, the patent enables uniform CMP processing across the entire wafer. Each recess region has optimized pattern density that prevents dishing and erosion, thereby improving manufacturing yield while maintaining the multi-voltage embedded memory functionality.
Data Source
AI summary
Various embodiments of the present application are directed to an IC device and associated forming methods. In some embodiments, a memory region and a logic region are integrated in a substrate. A memory cell structure is disposed on the memory region. A plurality of logic devices disposed on a plurality of logic sub-regions of the logic region. A first logic device is disposed on a first upper surface of a first logic sub-region. A second logic device is disposed on a second upper surface of a second logic sub-region. A third logic device is disposed on a third upper surface of a third logic sub-region. Heights of the first, second, and third upper surfaces of the logic sub-regions monotonically decrease. By arranging logic devices on multiple recessed positions of the substrate, design flexibility is improved and devices with multiple operation voltages are better suited.