Memory-on-Package Architecture With Embedded Stacks and Lower Z-Height
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Solution Overview
Problem
Existing Memory on Package (MoP) architectures face issues with increased Z-height and XY form factor due to the need for a memory package substrate, which also leads to signal integrity problems and high costs from using coreless or stiffener-based solutions.
Innovation Solution
The proposed solution involves embedding memory stacks directly in a mold layer on the package substrate with a die spanning across a cutout, eliminating the need for a separate memory package substrate and stiffener, thereby reducing Z-height and XY form factor while improving signal integrity through shorter interconnect lengths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a separate memory package substrate is used in MoP architecture, then memory stacking is enabled, but Z-height increases by 300-350 μm
Solution Approach 1:
The patent merges the memory stack assembly directly with the package substrate by embedding memory dies into recesses formed in the substrate. This eliminates the need for a separate memory package substrate, thereby reducing Z-height while maintaining memory stacking capability. The memory dies are positioned in recesses and connected via wire bonds or other interconnect structures integrated into the substrate.
Solution Approach 2:
The patent implements nesting by placing memory dies inside recesses (cavities) formed in the package substrate. This nested configuration allows the memory stack to be embedded within the substrate thickness rather than adding external height, achieving compact Z-dimension while preserving multi-layer memory stacking.
2Stability of the object's composition
If a stiffener is added to control warpage, then package substrate stability improves, but XY form factor increases
Solution Approach 1:
The patent combines the stiffener function with the package substrate itself by designing the substrate with an optimized core structure and layered construction that provides inherent stiffness. The substrate includes multiple layers with different material properties that work together to control warpage without requiring a separate stiffener component, thus maintaining compact XY footprint.
Solution Approach 2:
The patent employs composite material structures in the package substrate, combining multiple materials with different mechanical properties (e.g., rigid and flexible layers) to achieve optimal warpage control. This composite construction provides the necessary structural stability without adding external stiffeners that would increase the XY form factor.
3Length of stationary object
If a coreless package architecture is used to mitigate Z-height increase, then Z-height is reduced, but manufacturing cost increases significantly
Solution Approach 1:
The patent merges the memory stack with a standard cored package substrate, utilizing conventional substrate manufacturing processes. This approach maintains compatibility with existing manufacturing infrastructure, avoiding the high costs associated with coreless substrate fabrication while achieving reduced Z-height through the embedded memory configuration.
Solution Approach 2:
The patent introduces a mold compound as an intermediary material that encapsulates the memory dies and provides structural support. This mold compound enables the use of standard cored substrates while achieving the compact profile needed, serving as a cost-effective mediator between the memory stack and substrate without requiring expensive coreless architecture.
4Reliability
If memory dies are connected via wire bonds, then electrical connection is achieved, but interconnect length increases affecting signal integrity
Solution Approach 1:
The patent segments the interconnect path by using short wire bonds from each memory die to nearby contact pads on the substrate, rather than long interconnects spanning the entire package. This segmented approach minimizes individual interconnect lengths, improving signal integrity while maintaining reliable electrical connections.
Solution Approach 2:
The patent implements local quality by positioning contact pads in optimal locations on the substrate close to where the memory dies are embedded. This local placement of connection points minimizes wire bond lengths and interconnect traces, enhancing signal quality without compromising connection reliability.
Data Source
AI summary
Embodiments disclosed herein include an electronic package. In an embodiment, the electronic package comprises a package substrate with a cutout. In an embodiment, pads are adjacent to the cutout. In an embodiment, a memory die stack is on the package substrate, where the memory die stack is electrically coupled to the pads by routing in the package substrate. In an embodiment, a die is over the cutout, where the die is supported by the pads.