Embedded Memory Layout With Dummy Cells for Plasma Charge Dissipation
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Solution Overview
Problem
Emerging non-volatile memory technologies like RRAM, MRAM, and FeRAM face challenges due to plasma-induced damage during fabrication, which affects the performance and yield of previously-fabricated semiconductor devices such as FETs.
Innovation Solution
Incorporating a doped well in the substrate with a low resistance pathway for plasma charges to flow into, and forming dummy memory cells electrically coupled to the doped well, thereby protecting underlying devices from plasma-induced damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If plasma processes are used to fabricate emerging non-volatile memory devices, then memory device functionality is achieved, but plasma-induced damage occurs to previously-fabricated semiconductor devices
Solution Approach 1:
A dedicated plasma charge dissipation structure is introduced as an intermediary component between the plasma environment and the FETs. This structure provides a controlled pathway for plasma charges to dissipate, preventing direct damage to the FETs while allowing plasma processes to continue for memory device fabrication.
Solution Approach 2:
The harmful plasma charges that would normally damage FETs are redirected and utilized beneficially by the dissipation structure. The structure converts the harmful plasma charge accumulation into a controlled dissipation process, protecting the FETs while enabling continued plasma-based memory device fabrication.
2Object-affected harmful factors
If plasma charge dissipation pathways are added to protect FETs, then plasma-induced damage is reduced, but device structure complexity increases
Solution Approach 1:
The plasma charge dissipation function is segmented into a dedicated, separate structure rather than being integrated into the FET architecture. This allows the protection mechanism to operate independently without complicating the FET design, providing a clear functional separation between memory device fabrication and FET protection.
Solution Approach 2:
The dissipation structure uses simplified geometric forms (such as planar patterns or basic three-dimensional shapes) that can be replicated using standard photolithography and deposition techniques. This copying approach allows the protection structure to be manufactured with the same fabrication processes used for the memory devices themselves, minimizing additional process complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Reduces plasma-induced damage to semiconductor devices, leading to lower failure rates and higher yields by providing a pathway for plasma charges to dissipate safely, thus preserving the integrity of FETs and other underlying devices.
Implementation Method 1
plasma-induced damage during fabrication
Implementation Method 2
low resistance pathway for plasma charges to flow into
Data Source
AI summary
A semiconductor device and methods of fabrication thereof including a substrate, a doped well formed in the substrate, a transistor formed on the substrate, a dielectric material located over the doped well and the transistor and including interconnect structures extending through the dielectric material, the interconnect structures including a first set of interconnect structures electrically coupled to an active region of the transistor and a second set of interconnect structures electrically coupled to the doped well, an active memory cell electrically coupled to the active region of the transistor via the first set of interconnect structures; and a dummy memory cell electrically coupled to the doped well via the second set of conductive interconnect structures. The dummy memory cell and the second set of conductive interconnect structures may provide a low resistance pathway for plasma charge to flow to the doped well, thereby minimizing plasma induced damage to the transistor.