Embedded Memory Power-Up Sequencing via Programmable Logic
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Solution Overview
Problem
Current systems with embedded memories face challenges in mitigating in-rush current during power-up, leading to voltage droops that can cause circuit operation errors and require costly redesigns, as conventional sequencing methods are inflexible and prone to process variations.
Innovation Solution
A power-on sequencing circuit with a finite state machine and delay circuit dynamically determines the memory array and bank power-up sequence responsive to configuration signals, allowing for flexible adjustment of sequencing without locking in delays until after manufacturing, and uses a programmable logic circuit to minimize voltage droops.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional timed bits or buffer chains are used to sequence memory power-up, then in-rush current is reduced, but the sequencing is locked in before tape-out and cannot be adjusted for process variations
Solution Approach 1:
The patent implements a dynamic power-up sequencing mechanism using a finite state machine that can adjust the sequencing of memory banks based on configuration signals. Unlike conventional static approaches with fixed buffer chains, this system allows the designer to modify the power-up sequence after tape-out by changing configuration signals, thereby adapting to process variations without redesign.
Solution Approach 2:
The patent changes the parameter of sequencing delay by using programmable logic circuits that can be configured with different delay values. The finite state machine responds to configuration signals to generate appropriate delay periods between memory bank power-ups, allowing optimization of the power-up sequence to minimize voltage droop under various process conditions.
2Reliability
If too much delay is provided in memory sequencing to prevent voltage droop, then power-up reliability improves, but operation speed slows and power consumption increases
Solution Approach 1:
The patent applies partial action by providing just enough delay between memory bank power-ups to prevent voltage droop, rather than excessive delay. The finite state machine sequences memory banks with optimized delay periods that are sufficient to maintain voltage stability but minimal enough to preserve operation speed and reduce power consumption.
Solution Approach 2:
The system uses configuration signals that can be adjusted based on observed performance to optimize the power-up sequence. This feedback mechanism allows the designer to tune the delay periods to achieve the minimum necessary delay for voltage stability, thereby optimizing the trade-off between reliability and productivity.
3Ease of manufacture
If buffer chains are used for memory bank sequencing, then power-up sequencing is achieved, but circuit density is reduced due to the area occupied by buffers
Solution Approach 1:
The patent replaces the mechanical buffer chain approach with a logic-based finite state machine that uses configuration signals and programmable logic circuits to control power-up sequencing. This substitution eliminates the need for physical buffer chains, thereby reducing the circuit area while maintaining the power-up sequencing functionality.
4Loss of time
If memory banks are powered up simultaneously, then power-up time is minimized, but severe voltage droop occurs causing circuit reset
Solution Approach 1:
The patent segments the simultaneous power-up of all memory banks into a sequential process controlled by a finite state machine. The configuration signals divide the power-up event into staged transitions, where memory banks are powered up in a controlled sequence with optimized delays, minimizing the total power-up time while preventing severe voltage droop.
Data Source
AI summary
A programmable logic circuit such as a finite state machine is provided that is configured to determine a memory array power-up sequence from a configuration signal to successively enable each memory array. A delay circuit triggers an initial memory bank in each enabled memory array to power-up without a delay. The delay circuit then counts responsive to a clock to determine a delay between a successive triggering of remaining memory banks in each enabled memory array to power-up.