Embedded Memory Dielectric Cap Structure Using a Self-Assembled Monolayer
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Solution Overview
Problem
Embedded memory devices, particularly those using magnetic tunnel junctions, face damage during processing due to etching of the dielectric layer under the bottom electrode, leading to exposed and contaminated interconnects, which affects device integrity and performance.
Innovation Solution
A bi-layer dielectric cap structure is formed, with a self-assembled monolayer (SAM) selectively deposited over the memory stack to protect the dielectric cap layer during etching, followed by a second dielectric cap layer deposition, ensuring the SAM is not covered, thereby preventing dielectric layer removal and contamination.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single dielectric cap layer is used during etching, then the structure is simpler, but the dielectric layer under the bottom electrode is damaged or removed, exposing and contaminating interconnect lines
Solution Approach 1:
The dielectric cap is divided into two distinct layers: a first dielectric cap layer that remains during etching to protect the interconnect, and a second dielectric cap layer deposited afterward. This segmentation allows each layer to serve its specific function - the first layer protects during processing while the second provides final encapsulation, resolving the contradiction between structural simplicity and reliability.
Solution Approach 2:
The first dielectric cap layer is deposited in advance before the etching process to provide protective coverage over the interconnect structure. This preliminary action ensures that the interconnect is already protected when etching occurs, preventing damage and contamination that would otherwise occur with a single-layer structure.
2Ease of operation
If the dielectric cap layer is etched away during processing, then access to the memory stack is enabled, but the interconnect lines become exposed and contaminated
Solution Approach 1:
The first dielectric cap layer acts as an intermediary protective element between the etching process and the interconnect structure. It allows the etching to proceed and access the memory stack while simultaneously serving as a barrier that prevents harmful contaminants from reaching the interconnect, thus resolving the contradiction between accessibility and contamination protection.
3Reliability
If a self-assembled monolayer is formed over the memory stack, then the dielectric cap layer is protected during etching, but the structure becomes more complex
Solution Approach 1:
The self-assembled monolayer is formed through a self-organizing process where molecules automatically arrange themselves on the memory stack surface. This self-service mechanism provides protective coverage without requiring complex external intervention or additional processing equipment, thus achieving reliable dielectric protection while minimizing the increase in processing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively prevents dielectric layer damage and contamination, maintaining the integrity of the memory device structure and reducing the risk of junction shorts, while allowing for precise control of dielectric cap layer thickness, enhancing the reliability and performance of embedded memory devices.
Implementation Method 1
A self-assembled monolayer is formed over and in contact with the memory stack
Data Source
AI summary
A semiconductor device structure includes a metallization stack comprising one or more patterned metal layers. A bi-layer dielectric cap is disposed on and in contact with the metallization stack. At least one memory device is disposed on the bi-layer dielectric cap. A method for forming the metallization stack includes receiving a structure comprising a metallization layer and a first dielectric cap layer formed over the metallization layer. The metallization layer includes a logic area and a memory area. At least one memory stack is formed over the first dielectric cap layer. A self-assembled monolayer is formed over and in contact with the memory stack. A second dielectric cap layer is formed on and in contact with the first dielectric cap layer. The second dielectric cap layer is not formed on the self-assembled monolayer.