Embedded Memory Array Spare-Core Configuration
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Solution Overview
Problem
The challenge in semiconductor device manufacturing is to balance the need for embedded memory to meet performance requirements while maintaining yield and keeping manufacturing costs low, as conventional memory redundancy approaches often result in increased die size and defect rates due to the need for spare rows and columns, which can exceed available die space, especially in small or fragmented memory arrays.
Innovation Solution
The technique involves determining a spare-core configuration that eliminates or reduces memory row and column redundancies by calculating yield values based on global process parameters and design characteristics, allowing for the use of spare cores without redundant memory, thereby minimizing the size of embedded memory arrays and reducing defects during fabrication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional memory redundancy with spare rows and columns is implemented, then yield is maintained, but die size increases and defect rate increases
Solution Approach 1:
The patent segments the memory array into multiple bank groups, where each bank group contains multiple banks. This segmentation allows for more efficient redundancy management by enabling selective activation of banks based on defect locations, rather than requiring comprehensive spare rows and columns across the entire array. The segmented structure reduces the overall redundancy overhead while maintaining yield.
Solution Approach 2:
The patent introduces a new dimension of redundancy management by organizing memory into bank groups with multiple banks, adding a hierarchical layer between traditional row/column redundancy. This dimensional change allows defects to be managed at the bank level rather than requiring full array-wide spares, thereby reducing die size while maintaining reliability.
2Area of stationary object
If memory arrays are made smaller to reduce die size, then die space is saved, but the probability of defect increases
Solution Approach 1:
The patent merges multiple small memory banks into bank groups, where banks are closely spaced and share common control logic and redundancy resources. This merging approach allows small banks to benefit from shared redundancy mechanisms, reducing the need for individual spares in each small bank while maintaining defect coverage. The merged structure achieves better defect probability management compared to isolated small banks.
Solution Approach 2:
The patent implements universal redundancy resources that serve multiple banks within a bank group. The spare rows and columns are shared across banks, allowing a single set of spares to cover defects in any bank within the group. This multi-functional redundancy approach reduces the total redundancy overhead while maintaining protection against defects in small memory arrays.
3Productivity
If numerous embedded SRAM arrays are configured on a die, then performance is enhanced, but the need for redundancy increases die space requirements
Solution Approach 1:
The patent segments the die into multiple bank groups, each containing multiple embedded SRAM banks. This segmentation allows performance-critical arrays to be distributed across banks while using efficient redundancy management at the bank group level. The segmentation enables more arrays to fit on the die by reducing the space consumed by redundancy overhead in each array.
Solution Approach 2:
The patent changes the organizational parameters of memory arrays by introducing bank groups with multiple banks per group. This parameter change allows for denser packing of memory arrays on the die by optimizing the trade-off between array size, redundancy overhead, and defect coverage. The new organizational structure enables higher array density while maintaining acceptable yield.
Data Source
AI summary
Techniques are disclosed for achieving size reduction of embedded memory arrays through determining a spare-core layout. In an embodiment, input parameters comprising global process parameters are combined with design characteristics to compute yield values corresponding to potential redundancy configurations for a die. Resulting yields may be compared to determine which redundancy configuration is suitable to maintain a particular yield. A die configured with one or more spare cores (with no redundant memory therein) results in a yield which is equivalent to, or exceeds, the yield of a die with conventional memory redundancies. In some example cases, memory redundancy is eliminated from cores. Another embodiment provides a semiconductor structure having including an array of redundant cores, each including a composition of memory arrays and logic structures, wherein at least one of the memory arrays of each redundant core is implemented without at least one of row redundancy and column redundancy.