Embedded Memory Strap-Cell Layout With Lower Strap-Line Density
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Solution Overview
Problem
The integration of split-gate flash memory in embedded flash systems faces challenges due to high resistance in polysilicon and buried lines, leading to large voltage drops and reduced power efficiency, as well as complexity in design and scaling issues with multiple strap-cell types and extreme low k dielectric materials.
Innovation Solution
The implementation of a memory array with a reduced number of distinct strap-cell types, such as source line/erase gate, control gate/word line, and word-line strap cells, electrically coupled in different metallization layers to minimize voltage drops and allow for enhanced scaling and the use of extreme low k dielectric materials.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If polysilicon and buried lines are used for interconnect structures, then the memory array can be formed, but high resistance leads to large voltage drops and reduced power efficiency
Solution Approach 1:
The patent changes the material parameter of the interconnect structure from polysilicon to metal (such as copper or aluminum), which has significantly lower resistance. This parameter change directly reduces voltage drops and improves power efficiency in the memory array interconnect structures.
2Adaptability or versatility
If multiple strap-cell types are used, then comprehensive memory functions are achieved, but design complexity increases
Solution Approach 1:
The patent implements a unified strap-cell design that serves multiple functions: it acts as both a memory cell and a strap cell for different memory types (NAND, NOR, OLED). This universal design eliminates the need for multiple distinct strap-cell types, reducing design complexity while maintaining comprehensive memory functionality.
Solution Approach 2:
The patent merges the strap cell structure with the memory cell structure, combining functions that were previously separate. The strap cell integrates control gate, word line, and source line functionalities into a single unified structure, simplifying the overall design.
3Productivity
If extreme low k dielectric materials are used, then scaling is enabled, but device failure risk increases
Solution Approach 1:
The patent applies extreme low k dielectric materials selectively in specific regions where scaling is required, rather than throughout the entire device. This localized application enables scaling benefits while minimizing the risk of device failure associated with these materials.
Solution Approach 2:
The patent incorporates protective structures and design margins around the extreme low k dielectric regions to prevent device failure. This cushioning approach allows the use of aggressive scaling materials while maintaining reliability through preventive design measures.
Data Source
AI summary
Various embodiments of the present application are directed towards an integrated memory chip comprising a memory array with a strap-cell architecture that reduces the number of distinct strap-cell types and that reduces strap-line density. In some embodiments, the memory array is limited to three distinct types of strap cells: a source line/erase gate (SLEG) strap cell; a control gate/word line (CGWL) strap cell; and a word-line strap cell. The small number of distinct strap-cell types simplifies design of the memory array and further simplifies design of a corresponding interconnect structure. Further, in some embodiments, the three distinct strap-cell types electrically couple word lines, erase gates, and control gates to corresponding strap lines in different metallization layers of an interconnect structure. By spreading the strap lines amongst different metallization layers, strap-line density is reduced.