Embedded Memory Subsystems for CNN Processing Units
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Solution Overview
Problem
Existing CNN-based processing units are inefficient due to reliance on software solutions or hardware designed for general computation, leading to slow computational speeds and high costs, making them impractical for processing large imagery data, and existing memory technologies are not practical for integrating different memory types on a single silicon chip.
Innovation Solution
A CNN-based digital integrated circuit with embedded memory subsystems featuring a semi-conductor substrate containing CNN processing units with two types of MTJ STT-RAM cells, one for high retention and the other for balanced read/write operations, integrated with a controller and input/output data bus, fabricated using a method involving metal substrates, via layers, and high selectivity layers for etching support.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If software solutions or general-purpose hardware are used for CNN processing, then implementation flexibility is maintained, but computational speed becomes too slow and cost becomes too high for large imagery data processing
Solution Approach 1:
The processing system is segmented into multiple CNN processing units, each handling specific convolution operations independently. This parallel segmentation enables high-speed processing of large imagery data while maintaining manageable complexity through modular architecture
Solution Approach 2:
The patent replaces traditional software-based or general-purpose hardware processing with specialized hardware circuits designed specifically for CNN operations. This substitution of general computing mechanisms with domain-specific hardware achieves the required computational speed for real-time image processing
2Adaptability or versatility
If different memory technologies are integrated on a single silicon chip, then data storage requirements for different characteristics can be met, but manufacturing complexity increases
Solution Approach 1:
Different regions of the memory subsystem are assigned different memory technologies based on local requirements: Flash memory for filter coefficients requiring long-term retention, and SRAM for imagery data requiring frequent read/write operations. This local quality differentiation achieves versatile memory configuration while using standardized integration processes
Solution Approach 2:
The memory subsystem is designed with multi-functionality to handle different types of data with different characteristics using a unified control interface. The system can adaptively allocate and manage different memory technologies for different data types, achieving versatility without proportionally increasing manufacturing complexity
3Speed
If SRAM is used for storing imagery data, then fast read/write access is achieved, but retention rate is insufficient for long-term storage
Solution Approach 1:
The system uses an intermediary memory architecture where SRAM provides fast read/write access for active imagery data processing, while Flash memory serves as the retention medium for data that needs long-term storage. The memory controller acts as an intermediary managing data movement between these two memory types, achieving both speed and retention requirements
4Duration of action of stationary object
If Flash memory is used for storing filter coefficients, then long-term retention is achieved, but read/write endurance is insufficient for frequent operations
Solution Approach 1:
SRAM serves as an intermediary buffer between the Flash memory storing filter coefficients and the CNN processing units. Frequently accessed coefficients are loaded into SRAM for rapid repeated access, protecting the Flash memory from excessive write cycles and preserving its reliability while maintaining long-term retention capabilities
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables low-power, high-density, fast, and flexible processing-in-memory architecture with well-known manufacturing technologies, addressing the inefficiencies of prior art by optimizing memory usage and computational speed for large data processing.
Implementation Method 1
The memory subsystem includes first memory and second memory. The first memory contains an array of MTJ STT-RAM cells with each cell has a circular planar area with a diameter in a range of 40-120 nm. The second memory contains an array of MTJ STT-RAM cells with each cell has a circular planar area having a diameter in a range of 30-75 nm.
Implementation Method 2
fabrication method of an array of first magnetic tunnel junction (MTJ) elements and an array of second MTJ elements of an embedded memory subsystem
Data Source
AI summary
Embedded memory subsystems in a digital integrated circuit for artificial intelligence are disclosed. A semi-conductor substrate contains CNN processing units. Each CNN processing unit includes CNN logic circuits and an embedded memory subsystem. The memory subsystem includes first embedded memory and second embedded memory. The first embedded memory contains an array of MTJ STT-RAM cells with each cell has a circular planar area with a diameter in a range of 40-120 nm. The second embedded memory contains an array of MTJ STT-RAM cells with each cell has a circular planar area having a diameter in a range of 30-75 nm.