Embedded Memory Testing via Storage Borrowing
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Solution Overview
Problem
Conventional integrated circuit testing methods face inefficiencies due to the input/output bottleneck between on-chip processing capabilities and external testing equipment, leading to prolonged testing times and increased costs, especially as the number of transistors on integrated circuits increases.
Innovation Solution
The implementation of embedded memory testing within integrated circuits, where test logic borrows storage units from functional logic blocks to temporarily store memory test result data during the testing mode, allowing for uninterrupted testing and reduced need for additional memory, thereby addressing the input/output bottleneck.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If external automated testing equipment (ATE) is used to test integrated circuits, then comprehensive testing of all circuit devices can be performed, but testing time becomes extraordinarily long due to the limited number of input/output pads
Solution Approach 1:
The patent merges the testing function with the existing functional logic blocks by allowing them to serve dual purposes: performing their normal computational functions and simultaneously acting as test pattern generators and failure condition detectors. This eliminates the need for separate dedicated testing circuits and enables comprehensive testing without proportionally increasing the number of I/O pads required.
Solution Approach 2:
Functional logic blocks are designed to perform multiple functions: they generate test patterns, execute test algorithms, detect failures, and store test data. This multi-functionality allows the same circuit resources to be used for both normal operation and testing, thereby reducing the need for additional dedicated testing infrastructure and minimizing testing time.
2Productivity
If built-in self-test (BIST) logic is implemented to perform internal testing, then testing speed improves by avoiding the input/output bottleneck, but additional memory resources are required to store test data which increases device complexity
Solution Approach 1:
The patent combines the test data storage function with existing functional logic blocks that have idle computational resources. Instead of adding separate dedicated memory structures for BIST, the system utilizes the functional logic blocks' existing storage and processing capabilities to hold test patterns, intermediate results, and failure conditions, thereby avoiding additional memory overhead.
Solution Approach 2:
The functional logic blocks temporarily borrow computational and storage resources during testing modes, performing test functions when not needed for normal operations. After testing completes, these resources are recovered and returned to their primary functional用途, ensuring that additional permanent memory resources are not required.
3Adaptability or versatility
If the number of transistors on integrated circuits increases to provide more processing capabilities, then on-chip processing capabilities improve, but the number of available input/output pads remains constrained by physical limitations
Solution Approach 1:
The patent introduces an intermediary approach where functional logic blocks act as mediators between the internal circuit devices and external testing equipment. These logic blocks generate test patterns internally and process test results, reducing the need for direct I/O pad connections to every circuit device and thereby mitigating the impact of limited I/O pads despite increased transistor counts.
Data Source
AI summary
An integrated circuit (IC) is disclosed herein for embedded memory testing with storage borrowing. In an example aspect, an integrated circuit includes a functional logic block, a memory block, and test logic. The functional logic block includes multiple storage units and is configured to store functional data in the multiple storage units during a regular operational mode. The test logic is configured to perform a test on the memory block during a testing mode. The test logic is also configured to retain memory test result data in the multiple storage units of the functional logic block during the testing mode.