Embedded-Memory Trench-Gate HV Transistor for Gate Metal Protection
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Solution Overview
Problem
The integration of high voltage devices in embedded memory ICs faces challenges due to manufacturing issues such as poor device height uniformity and gate metal loss during planarization, leading to sheet resistance and threshold voltage variations.
Innovation Solution
The implementation of a trench gate high voltage transistor design, where the logic gate dielectric and electrode are positioned within a trench, reducing lateral device area and protecting the top surface from planarization processes, thereby maintaining device integrity and uniformity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If high voltage devices are integrated in embedded memory ICs using conventional planar structures, then device functionality is achieved, but poor device height uniformity and gate metal loss occur during planarization
Solution Approach 1:
The patent transitions from a conventional planar gate structure to a trench gate structure, moving the gate electrode into a vertical dimension by etching a trench into the substrate. This dimensional change allows the gate to be positioned at a lower level, protecting it from planarization damage while maintaining electrical functionality, thereby resolving the contradiction between manufacturing precision and reliability
Solution Approach 2:
The gate electrode is nested within the trench structure, with the gate dielectric layer surrounding the gate electrode in the trench. This nested configuration protects the gate metal from exposure during planarization processes, preventing gate metal loss while maintaining device height uniformity across the chip
2Ease of manufacture
If conventional planar gate structures are used, then manufacturing process is simpler, but sheet resistance and threshold voltage variations increase
Solution Approach 1:
By moving the gate structure into a vertical trench configuration, the patent achieves better control over gate positioning and dimensions. This dimensional transition enables more precise control of gate length and width, resulting in improved sheet resistance uniformity and threshold voltage consistency across devices
3Area of moving object
If device lateral area is reduced for compactness, then integration density improves, but device performance may be compromised
Solution Approach 1:
The trench gate structure utilizes the vertical dimension by etching into the substrate, allowing the gate to extend downward rather than requiring larger lateral dimensions. This enables compact lateral footprint while maintaining sufficient gate area for consistent device performance through controlled gate length and width in the vertical configuration
Data Source
AI summary
Various embodiments of the present application are directed to an IC, and associated forming methods. In some embodiments, the IC is manufactured by forming a plurality of deep trenches including an isolation trench and a logic device trench from a top surface of a substrate, filling an isolation material in the isolation trench and the logic device trench, removing the isolation material from the logic device trench, forming a first logic device by filling a first logic gate dielectric and a first logic gate electrode in the logic device trench, and forming first and second source/drain regions in the substrate on opposite sides of the logic device trench. The isolation material is kept in the isolation trench to form an isolation structure.