Embedded Metal Bitlines for Low-Resistance 3D Memory Stacks
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Solution Overview
Problem
Current memory technologies face challenges in creating buried bitlines (BLs) that meet performance requirements, particularly in three-dimensional integration, where reducing interconnect wire length and power consumption are essential.
Innovation Solution
The creation of metal bitlines on the bottom surface of wafers using techniques such as the salicide process or damascene process, which involves depositing a transition metal layer, reacting it with silicon to form a low-resistance silicide, and then isolating the metal bitlines within trenches, allows for reduced resistance and increased performance in memory devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional non-metal buried bitlines are used in three-dimensional memory integration, then manufacturing complexity is reduced, but resistance is high and performance requirements are not met
Solution Approach 1:
The patent changes the material parameter of the bitline from traditional non-metal materials to metal materials (such as copper, tungsten, or cobalt), which fundamentally alters the electrical resistance characteristic. This material parameter change enables the bitline to meet performance requirements by achieving lower resistance, while the metal materials selected are compatible with existing semiconductor manufacturing processes
Solution Approach 2:
The patent employs composite structure by combining metal bitline material with the surrounding dielectric and silicon substrate. The metal bitline is embedded within trenches filled with dielectric material, creating a composite structure that provides both low resistance conduction path and proper electrical isolation, thus meeting performance requirements while integrating with existing manufacturing processes
2Reliability
If metal bitlines are created using salicide or damascene processes, then resistance is reduced and performance is improved, but manufacturing complexity increases
Solution Approach 1:
The patent applies preliminary action by forming the metal bitline structure (either through salicide deposition or damascene trench creation) before finalizing the memory device assembly. The bitline material is deposited and patterned in advance, and the surrounding dielectric is subsequently formed to complete the embedding process, allowing for controlled resistance reduction while managing manufacturing complexity through staged processing
Solution Approach 2:
The patent uses intermediary materials and processes to bridge the gap between simple manufacturing and low resistance. In the damascene approach, a dielectric intermediary material is deposited around the metal bitline to provide isolation while allowing the metal to maintain its low resistance path. In the salicide approach, a silicide formation process acts as an intermediary step that converts deposited metal into a low-resistance compound
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The use of metal bitlines reduces resistance and enhances the performance of memory devices, enabling more efficient three-dimensional memory structures with improved conductivity and reduced power consumption.
Implementation Method 1
reacting it with silicon to form a low-resistance silicide
Data Source
AI summary
Techniques are disclosed herein for creating metal bitlines (BLs) in stacked wafer memory. Using techniques described herein, metal BLs are created on a bottom surface of a wafer. The metal BLs can be created using different processes. In some configurations, a salicide process is utilized. In other configurations, a damascene process is utilized. Using metal reduces the resistance of the BLs as compared to using non-metal diffused BLs. In some configurations, wafers are stacked and bonded together to form three-dimensional memory structures.