Embedded Metal Bump Reinforcement for Fine-Pitch Packaging Substrates
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Solution Overview
Problem
Semiconductor packaging substrates, particularly coreless substrates with Ajinomoto build-up film (ABF) materials, face mechanical weakness and challenges in achieving fine bump pitch due to conventional solder on pad (SOP) surface finishes, leading to issues like via or trace cracking during thermal cycling and inconsistent underfill volume.
Innovation Solution
The implementation of patterned metal base layers with surface mount (SMT) metal bumps and metal dam structures, formed using an etch-back technique, which are partially embedded within and protrude from the build-up structure, providing structural reinforcement and allowing for finer bump pitch without additional mechanical support or glass reinforcement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If coreless substrates with ABF materials are used to make thin dielectric layers, then substrate thickness is reduced, but mechanical strength deteriorates
Solution Approach 1:
The substrate structure is segmented into multiple functional layers: thin dielectric layers for electrical isolation and metal bump structures with embedded patterned metal base layers for mechanical reinforcement. This segmentation allows each layer to optimize its specific function while collectively providing both thinness and strength.
Solution Approach 2:
The invention uses composite structures combining dielectric materials (ABF) with metal reinforcement elements (patterned metal base layer, metal bumps, metal dam structures). This composite approach integrates the electrical properties of dielectrics with the mechanical strength of metals, resolving the contradiction between thinness and mechanical strength.
2Ease of manufacture
If conventional solder on pad surface finishes are used, then manufacturing process is simple, but bump pitch is limited to greater than 100 μm
Solution Approach 1:
The invention replaces the conventional SOP surface finish mechanism with SMT metal bump technology. This substitution enables fine pitch applications by using metal bump formation processes that can achieve smaller pitch dimensions while maintaining manufacturing feasibility through established SMT processes.
3Volume of moving object
If thin substrates without thick inner core are used, then substrate thickness is reduced, but resistance to mechanical stress deteriorates
Solution Approach 1:
Instead of uniformly thickening the entire substrate, the invention applies metal reinforcement elements locally at critical positions where mechanical stress occurs. The patterned metal base layer is strategically positioned to provide reinforcement exactly where needed, maintaining thin overall substrate thickness while providing localized mechanical strength.
Solution Approach 2:
The patterned metal base layer is formed and embedded within the dielectric layers during the substrate fabrication process, before the substrate is assembled into the final package. This preliminary reinforcement ensures mechanical strength is built-in from the beginning, preventing stress-related failures before they occur.
4Strength
If patterned metal base layer is partially embedded within build-up structure, then mechanical integrity is enhanced, but manufacturing complexity increases
Solution Approach 1:
The invention merges the formation of the patterned metal base layer with the existing dielectric layer build-up process. The metal base layer is integrated into the lamination and etching sequences already used for creating dielectric layers, combining multiple functions into a unified manufacturing flow rather than adding separate processing steps.
Data Source
AI summary
Semiconductor packaging substrates and processing sequences are described. In an embodiment, a packaging substrate includes a build-up structure, and a patterned metal contact layer partially embedded within the build-up structure and protruding from the build-up structure. The patterned metal contact layer may include an array of surface mount (SMT) metal bumps in a chip mount area, a metal dam structure or combination thereof.


