Embedded MIB Capacitor Layout for Low-Impedance IC Packages

The patent transitions from planar interconnect layouts to three-dimensional stacked architectures, utilizing vertical vias and multiple layers to route power and ground signals in different spatial dimensions. This dimensional change allows high interconnect density while minimizing planar loop areas that cause inductance, thereby resolving the contradiction between density and power-delivery performance

The patent implements nested power delivery structures where ground vias are positioned within or adjacent to power vias, creating concentric or nested current paths. This nesting approach minimizes the loop area between power and ground returns, reducing inductance while maintaining high interconnect density in the multi-chip package

The patent utilizes the vertical dimension by embedding passive devices within the substrate layers and connecting them through via structures rather than requiring lateral placement. This vertical integration allows passive devices to be positioned close to dice in the Z-direction while maintaining manageable manufacturing processes, thereby improving power delivery efficiency without excessively increasing assembly complexity

The patent combines passive devices with the substrate structure itself, integrating capacitors and other components directly into the substrate layers rather than as separate surface-mounted elements. This merging approach reduces the distance between passive devices and dice, improving power delivery efficiency while consolidating manufacturing steps