Embedded Microfluidic Channels in Semiconductor Chips
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Solution Overview
Problem
Current methods for integrating microfluidics with CMOS chips are complex, affecting yield, process time, alignment accuracy, and design flexibility, and require benchtop instruments for signal reading, limiting the convenience of point-of-care applications.
Innovation Solution
A semiconductor chip with embedded microfluidic channels is fabricated using a wet etching process that removes metal layers and bridge patterns to form connected microfluidic channels and via holes, integrating well with the semiconductor manufacturing process, reducing manufacturing costs and enhancing precision and complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If modular components are used to integrate microfluidics and CMOS, then design flexibility is improved, but manufacturing complexity increases due to post-CMOS lithography or wafer bonding steps
Solution Approach 1:
The patent merges the microfluidic channel formation with the CMOS manufacturing process by using the same lithography and etching steps to create both circuit patterns and microfluidic channels. The metal layers serve dual purposes: as electrical interconnects in CMOS and as structural walls defining microfluidic channels. This eliminates separate post-CMOS lithography or wafer bonding steps, reducing manufacturing complexity while maintaining design flexibility.
Solution Approach 2:
The patent applies multi-functionality by designing metal layers that simultaneously serve electrical interconnect functions in CMOS circuits and structural wall functions for microfluidic channels. The same lithography patterns define both circuit traces and channel boundaries, allowing a single manufacturing process to achieve both electronic and fluidic functionality without additional specialized steps.
2Reliability
If post-CMOS lithography or wafer bonding is used to integrate microfluidics, then integration is achieved, but alignment accuracy is reduced and process time increases
Solution Approach 1:
The patent performs the microfluidic channel definition actions during the CMOS manufacturing process itself, rather than as a subsequent step. The lithography and etching patterns are established in advance during standard CMOS fabrication, ensuring precise alignment with circuit features. This preliminary action eliminates the need for separate alignment steps later in the process.
Solution Approach 2:
By combining the microfluidic channel formation with CMOS manufacturing steps, the patent eliminates sequential processes that would require separate alignment. The same lithography and etching operations define both circuit patterns and microfluidic channels simultaneously, achieving integration without compromising alignment accuracy or increasing process time.
3Difficulty of detecting and measuring
If benchtop instruments are used to read biosensor signals, then signal reading capability is maintained, but convenience for point-of-care applications is reduced
Solution Approach 1:
The patent merges the microfluidic device with CMOS components that provide electronic signal processing and readout capabilities directly on the chip. This integration eliminates the need for separate benchtop instruments by incorporating amplifiers, detectors, and signal processing circuits within the same device, enabling portable point-of-care applications while maintaining sophisticated signal reading capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The integration of microfluidic structures with semiconductor chips improves cost-efficiency, precision, and complexity, enabling more effective and convenient point-of-care applications without the need for benchtop instruments.
Implementation Method 1
performing a wet etching process to remove part of the first metal layer, part of the second metal layer and one of the first bridge patterns
Data Source
AI summary
A semiconductor chip with embedded microfluidic channels includes a semiconductor substrate, a circuit structure layer, a first microfluidic channel and a micro via hole. The circuit structure layer includes a first metal layer, a first insulation layer and a second metal layer sequentially disposed on a substrate surface of the semiconductor substrate along a stacking direction. A plurality of first bridge patterns penetrates the first insulation layer, and are each electrically connected to the first metal layer and/or the second metal layer. The first microfluidic channel and the micro via hole are embedded in the circuit structure layer. In the stacking direction, a first height of the first microfluidic channel is equal to a first thickness of the first metal layer. In any direction parallel to the substrate surface, a hole width of the micro via hole is equal to a pattern width of each of the first bridge patterns.