Embedded Microprocessor Code Protection via Salted Hash Cache Authentication
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Solution Overview
Problem
Embedded micro-processors face challenges in protecting code from unauthorized alteration, especially in cost-sensitive and power-sensitive applications where minimizing embedded RAM is necessary, leading to vulnerabilities such as 'man-in-the-middle' attacks and security risks.
Innovation Solution
A method that involves reading immutable boot code from ROM, calculating and authenticating a hash of external code using a true random number generator (TRNG) and storing salted hashes in an internal hash table, allowing secure caching and real-time detection of code alterations, thereby preventing unauthorized changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If embedded RAM is minimized to reduce cost and power consumption, then cost sensitivity and power sensitivity are improved, but code security against unauthorized alteration deteriorates
Solution Approach 1:
The code storage is segmented into multiple cache lines, each independently authenticated with its own hash value stored in a hash table. This allows selective authentication of individual code segments without requiring full RAM protection, reducing overall security overhead while maintaining code integrity.
Solution Approach 2:
Hash values for all cache lines are pre-calculated and stored in a hash table before code execution. This preliminary authentication setup enables rapid verification of cache lines during runtime without requiring additional computational resources, securing code while minimizing RAM usage.
2Use of energy by stationary object
If embedded RAM is minimized to reduce power consumption, then power sensitivity is improved, but code security against unauthorized alteration deteriorates
Solution Approach 1:
Instead of protecting all code in RAM, only critical cache lines are authenticated using the hash table mechanism. This partial protection approach provides sufficient security for security-critical code segments while avoiding the power overhead of protecting entire code bases, thus reducing power consumption while maintaining adequate security.
3Quantity of substance
If external memory is used to replace embedded memory, then embedded RAM is reduced, but execution speed deteriorates due to slower external memory access
Solution Approach 1:
Code is pre-loaded from external memory into cache during system initialization or idle periods. The hash table is also pre-populated with authentication values for these cache lines. This preliminary action enables fast execution from cache during runtime without requiring continuous external memory access, thus maintaining execution speed while using minimal embedded RAM.
4Quantity of substance
If cache is used to minimize embedded RAM, then embedded RAM is reduced, but security against man-in-the-middle attacks deteriorates
Solution Approach 1:
A feedback mechanism continuously monitors cache line integrity by comparing current cache line hashes against the pre-stored hash table values. When a cache miss occurs or suspected tampering is detected, the system retrieves the cache line from external memory, re-authenticates it using the hash table, and updates the cache only if authentication succeeds. This feedback loop detects and prevents man-in-the-middle attacks while maintaining efficient cache operation with minimal embedded RAM.
Data Source
AI summary
A method to protect code against altering includes reading immutable boot code from a ROM. A code image is loaded from an external memory and a hash is calculated by a core unit. The hash is initially authenticated using the boot code for decrypting the hash of the external memory. A salted hash for each equivalent of a cache line of the code image is concurrently calculated by a cache protection block and the salted hash for each cache line in an internal hash table is stored. If the authentication succeeds, a part of the code image is loaded into a secure cache of the embedded micro-processor.


