Embedded MIM Capacitor for 3D IC Package Interconnect Delay
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Solution Overview
Problem
Decoupling capacitors integrated into chips using surface-mount technology (SMT) suffer from long external interconnects, leading to increased time delays in voltage spike suppression due to longer connection lengths, which can be improved by integrating them into 3D IC packaging structures like CoWoS and InFO, where internal interconnects are shorter, allowing for higher capacitance, reduced power consumption, improved operational speed, and reduced packaging footprint.
Innovation Solution
A method for forming a metal insulator metal (MIM) decoupling capacitor within 3D IC packaging, such as InFO, involving a glass carrier substrate with a protective layer, redistribution layers, through interposer vias, and a high-dielectric constant dielectric material, enabling shorter interconnects and higher capacitance values.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If decoupling capacitors are integrated using surface-mount technology (SMT), then ease of manufacture is improved, but interconnect length increases leading to time delays
Solution Approach 1:
The patent merges the decoupling capacitor integration into the 3D IC packaging structure itself, combining what were previously separate components (capacitor and interconnect) into a unified internal structure. This eliminates the need for external SMT mounting and reduces interconnect length to minimal internal traces, resolving the contradiction between ease of manufacture and time delays.
Solution Approach 2:
The patent transitions from 2D surface-mount integration to 3D volumetric integration within the packaging structure. By utilizing the vertical dimension and internal packaging volume, the capacitor can be positioned much closer to the power consumption sources, dramatically reducing interconnect length while maintaining manufacturing feasibility through established 3D packaging processes.
2Speed
If decoupling capacitors are integrated into 3D IC packaging, then interconnect length is reduced improving speed, but device complexity increases
Solution Approach 1:
The patent creates a multi-functional packaging structure that simultaneously serves as mechanical support, electrical interconnect, and capacitor housing. The packaging substrate performs multiple roles including structural foundation, signal routing, and capacitor integration platform, reducing overall device complexity despite the advanced integration by consolidating functions into unified structures.
Solution Approach 2:
The patent segments the packaging structure into modular functional regions including dedicated capacitor regions, interconnect layers, and mounting areas. This segmentation allows for systematic design and manufacturing while achieving short interconnects, balancing speed improvement with manageable device complexity through organized structural division.
3Area of stationary object
If traditional SMT capacitors are used, then packaging footprint is larger, but capacitance value is limited
Solution Approach 1:
The patent nests the decoupling capacitor within the internal volume of the 3D IC packaging structure, placing the capacitor between functional layers rather than mounting it externally. This nesting approach utilizes the three-dimensional space efficiently, achieving high capacitance values while minimizing the external packaging footprint by eliminating wasted external mounting space.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The integration of MIM capacitors into 3D IC packaging reduces time delays, enhances capacitance, minimizes power consumption, improves operational speed, and decreases packaging size compared to traditional SMT methods.
Implementation Method 1
a high-dielectric constant dielectric material disposed between the first metal layer and the second metal layer
Data Source
AI summary
The present disclosure describes a method of forming a metal insulator metal (MIM) decoupling capacitor that can be integrated (or embedded) into a 3D integrated circuit package such as, for example, a chip-on-wafer-on-substrate (CoWoS) chip package or an integrated fan-out (InFO) chip package. For example, the method includes providing a glass carrier with a protective layer over the glass carrier. The method also includes forming a capacitor on the protective layer by: forming a bottom metal layer on a portion of the protective layer; forming one or more first metal contacts and a second metal contact on the bottom metal layer, where the one or more first metal contacts have a width larger than the second metal contact; forming a dielectric layer on the one or more first metal contacts; and forming a top metal layer on the dielectric layer.