Embedded MIM Decoupling Capacitor Structure for 3D IC Packaging
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Solution Overview
Problem
Decoupling capacitors integrated via surface-mount technology (SMT) on packaging substrates result in long external interconnects, leading to increased time delay, reduced capacitance, higher power consumption, and larger packaging footprint due to external connections.
Innovation Solution
Integrate decoupling capacitors as metal-insulator-metal (MIM) structures within 3D integrated circuit (IC) packaging, utilizing high-dielectric constant materials and internal interconnects to reduce time delay, enhance capacitance, and minimize packaging size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If decoupling capacitors are integrated via surface-mount technology (SMT) on packaging substrates, then the capacitors can be added to the package, but long external interconnects result in increased time delay and reduced capacitance
Solution Approach 1:
The patent merges the decoupling capacitor integration into the 3D IC packaging process itself, combining the capacitor formation with the interconnect structure. This eliminates the need for separate SMT mounting and long external interconnects by integrating the capacitor directly onto the interposer substrate within the packaging architecture, thereby reducing time delay while maintaining decoupling capability
Solution Approach 2:
The patent transitions from traditional 2D surface-mount capacitor placement to 3D integrated capacitor structures within the packaging volume. By utilizing vertical stacking and three-dimensional interconnect pathways through the interposer substrate, the capacitor is positioned much closer to the die, reducing the effective interconnect length and time delay in the third dimension
2Reliability
If decoupling capacitors are mounted externally via SMT, then the capacitors can be added to the package, but the packaging footprint increases due to external connections
Solution Approach 1:
The patent combines the decoupling capacitor function with the existing packaging substrate and interconnect structure. By integrating the capacitor onto the interposer rather than mounting it externally, the packaging footprint is reduced as the capacitor occupies space within the existing package volume rather than adding to the external footprint
3Reliability
If decoupling capacitors are integrated in the far back end of the line during or after packaging, then the capacitors can be added, but the interconnect length increases leading to higher power consumption
Solution Approach 1:
The patent performs capacitor integration and interconnect formation as preliminary actions during the core packaging process rather than as a final back-end step. By forming the capacitor structures and their interconnects simultaneously with the packaging architecture, the interconnect length is minimized from the outset, reducing the resistance and power consumption associated with long trailing interconnects
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The integrated MIM capacitors in 3D IC packaging reduce time delay, increase capacitance, lower power consumption, and decrease packaging size, while maintaining operational speed.
Implementation Method 1
a capacitor dielectric layer disposed between the at least one first through-via and the electrode layer to separate the at least one first through-via from the electrode layer
Data Source
AI summary
A package having a capacitor structure and a method of forming the same are provided. The package includes a first die; a second die bonded onto the first die; an isolation region disposed on the first die and laterally encapsulating the second die; at least one first through-via disposed aside the second die and penetrating through the isolation region; an electrode layer disposed on the at least one first through-via; and a capacitor dielectric layer disposed between the at least one first through-via and the electrode layer to separate the at least one first through-via from the electrode layer, wherein the at least one first through-via, the capacitor dielectric layer, and the electrode layer constitute a capacitor structure.