Embedded MIM Capacitor Die Layout for Package Power Delivery
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Solution Overview
Problem
Existing decoupling capacitor solutions, such as on-die and package level capacitors, face challenges in providing effective decoupling capacitance due to distance and location constraints, particularly in complex die architectures like multi-die tiling and large single die configurations, leading to deficiencies in power delivery performance.
Innovation Solution
Embedding a metal-insulator-metal (MIM) capacitor die in the package substrate directly underneath the surface mount die, allowing for short and direct connections to power delivery interface circuitry, thereby enhancing decoupling capacitance and power delivery performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If package level decoupling capacitors are used, then decoupling capacitance is provided, but distance and location constraints prevent positioning close enough to PHY areas for optimal power delivery performance
Solution Approach 1:
The capacitor die is embedded within the package substrate itself, nesting the decoupling function inside the package structure rather than placing it externally. This allows the capacitor to be positioned in close proximity to the PHY areas while maintaining the benefits of package-level implementation.
Solution Approach 2:
The solution transitions from planar placement constraints to three-dimensional embedding within the package substrate layers. By utilizing the vertical dimension and internal substrate space, the capacitor can be positioned optimally close to power delivery interfaces without being constrained by surface area limitations.
2Object-affected harmful factors
If on-die MIM capacitors are used, then high-frequency noise is reduced, but die area constraints and floor planning limitations lead to capacitance deficiencies
Solution Approach 1:
The capacitor function is extracted from the die itself and placed in a separate capacitor die within the package substrate. This separation allows the processor die to maintain its floor plan without capacitor area constraints while still providing effective decoupling close to the PHY areas through the embedded package-level capacitor.
3Ease of manufacture
If package level capacitors are positioned far from PHY areas, then manufacturing is simplified, but power delivery performance deteriorates due to distance constraints
Solution Approach 1:
The package substrate is segmented into functional regions, with the capacitor die embedded in a specific location optimized for power delivery performance. This segmentation allows independent optimization of the capacitor placement near PHY areas while maintaining standard manufacturing processes for the overall package structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The embedded MIM capacitor die provides improved power delivery performance by minimizing distance to power delivery interfaces, reducing AC resonance impedance, and offering scalable capacitance without increasing die size or cost, addressing deficiencies in conventional solutions.
Implementation Method 1
a capacitor die embedded in the package substrate... providing capacitance to a surface mounted die
Implementation Method 2
embedding a metal-insulator-metal (MIM) capacitor die in the package substrate
Data Source
AI summary
A package substrate is disclosed. The package substrate includes a die package in the package substrate located at least partially underneath a location of a power delivery interface in a die that is coupled to the surface of the package substrate. Connection terminals are accessible on a surface of the die package to provide connection to the die that is coupled to the surface of the package substrate. Metal-insulator-metal layers inside the die package are coupled to the connection terminals.