Embedded MIM Capacitor Via Segmentation
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Solution Overview
Problem
The existing MIM capacitors of embedded structures face challenges in performance and reliability due to over-etching issues during via formation, which affects the capacitor upper electrode and insulating dielectric layer.
Innovation Solution
The MIM capacitor is formed with a stack structure on an interlayer film, where the capacitor lower electrode is connected to the first metal wire layer via a via, and the upper electrode is directly connected to the second metal wire layer, with a side wall isolating the lower electrode from the second metal wire layer, eliminating the need for a top via and thus avoiding etching impacts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If vias are formed using the same etching process at the same time, then the manufacturing process is simplified, but the capacitor upper electrode and insulating dielectric layer are damaged due to over-etching
Solution Approach 1:
The patent divides the via formation process into two separate stages: first forming the lower electrode via, then forming the upper electrode via. This segmentation allows different etching parameters to be used for each via type, preventing over-etching damage to the capacitor components while maintaining manufacturing efficiency.
Solution Approach 2:
The lower electrode via is formed first before the capacitor structure is complete, and the upper electrode via is formed later after the capacitor is assembled. This preliminary action sequence allows the etching process to be controlled at different stages, avoiding the need to compromise between via depth requirements and capacitor protection.
2Reliability
If the via depth is increased to reach the first metal wire layer, then the electrical connection is improved, but the etching process becomes harder to control and causes over-etching
Solution Approach 1:
The deep via formation is segmented into two separate via formation processes. The first via (lower electrode via) is formed to the required depth with controlled etching, and the second via (upper electrode via) is formed separately with different etching parameters. This segmentation makes the deep etching process controllable and prevents over-etching.
Solution Approach 2:
Different etching parameters and conditions are applied to different via locations and stages. The lower electrode via uses etching parameters optimized for reaching the first metal wire layer, while the upper electrode via uses parameters optimized for connecting to the capacitor upper electrode without damaging surrounding structures.
Data Source
AI summary
The present application has disclosed an MIM capacitor of an embedded structure, wherein an interlayer film is formed between a first metal wire layer and a second metal wire layer; the MIM capacitor is formed on the surface of the interlayer film; a capacitor lower electrode is connected to the first metal wire layer by means of a bottom first via, the first metal wire layer is connected, by means of a second via outside the capacitor lower electrode, to a lower electrode lead-out structure formed by the second metal wire layer; and an upper electrode lead-out structure formed by the second metal wire layer covers the surface of the capacitor upper electrode of the MIM capacitor. The present application has further disclosed a method for manufacturing an MIM capacitor of an embedded structure. In the present application, the performance and stability of the capacitor can be improved.