Embedded MIM Decoupling Capacitors for Low-Delay 3D IC Packaging
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Solution Overview
Problem
Decoupling capacitors integrated into chips using surface-mount technology (SMT) suffer from increased time delays due to external interconnects, which can lead to voltage spikes during power demand changes, and have limitations in capacitance range and power consumption.
Innovation Solution
The integration of metal insulator metal (MIM) decoupling capacitors within 3D IC packaging structures, such as chip-on-wafer-on-substrate (CoWoS) or integrated fan-out (InFO) packages, utilizing high dielectric constant materials and internal interconnects to reduce time delays, increase capacitance, and improve operational speed while minimizing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If surface-mount technology (SMT) is used to integrate decoupling capacitors, then ease of manufacture is improved, but time delay increases due to external interconnects
Solution Approach 1:
The patent merges the decoupling capacitor integration into the 3D IC packaging structure itself, eliminating the need for separate SMT mounting. The capacitors are formed as embedded structures within the packaging layers, directly connecting to the chip interconnects, thereby reducing time delay while maintaining manufacturing efficiency through integrated fabrication processes.
Solution Approach 2:
The patent transitions from planar SMT mounting to three-dimensional embedded integration within the packaging structure. By utilizing vertical stacking and internal routing layers in the 3D IC package, the capacitors are positioned closer to the power consumption sources, reducing interconnect length and time delay while maintaining ease of manufacture through additive fabrication steps.
2Ease of manufacture
If surface-mount technology (SMT) is used to integrate decoupling capacitors, then ease of manufacture is improved, but capacitance range is limited
Solution Approach 1:
The patent enables capacitance value adjustment by varying key parameters of the embedded capacitor structures, including the surface area of the capacitor plates, the thickness of the dielectric material, and the dielectric constant of the insulator. These parameter changes allow tuning of capacitance across a wide range while maintaining compatibility with standard 3D IC packaging fabrication processes.
Solution Approach 2:
The patent employs composite material structures for the embedded capacitors, combining different dielectric materials with varying dielectric constants to achieve desired capacitance values. The use of high-k dielectric materials combined with standard packaging materials enables extended capacitance range while maintaining ease of manufacture through established material deposition techniques.
3Ease of manufacture
If surface-mount technology (SMT) is used to integrate decoupling capacitors, then ease of manufacture is improved, but power consumption increases
Solution Approach 1:
By merging the decoupling capacitor function into the internal 3D IC packaging structure, the patent eliminates power losses associated with external interconnects and SMT mounting. The embedded capacitors are positioned adjacent to power consumption sources, reducing the energy dissipated in interconnect resistance and improving overall power efficiency while maintaining ease of manufacture through integrated fabrication.
4Loss of time
If embedded MIM capacitors are integrated into 3D IC packaging, then time delay is reduced, but device complexity increases
Solution Approach 1:
The patent designs the embedded MIM capacitor structures to serve multiple functions within the 3D IC packaging, including decoupling, signal filtering, and impedance matching. By making these structures multi-functional, the patent reduces time delay without proportionally increasing device complexity, as the same structural elements perform multiple roles in the packaging system.
Solution Approach 2:
The patent divides the 3D IC packaging structure into discrete functional layers, with capacitor-forming layers interspersed among the interconnect layers. This segmentation allows for modular fabrication processes where capacitor structures are formed in specific stages, reducing overall device complexity by breaking down the integration process into manageable segments while achieving reduced time delay through close proximity to power sources.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces time delays, enhances capacitance range, lowers power consumption, and decreases packaging footprint, effectively suppressing voltage spikes and improving operational speed by leveraging internal interconnects and high-k dielectric materials.
Implementation Method 1
utilizing high dielectric constant materials
Data Source
AI summary
The present disclosure is directed to a method for forming metal insulator metal decoupling capacitors with scalable capacitance. The method can include forming a first redistribution layer with metal lines on a portion of a polymer layer, depositing a photoresist layer on the first redistribution layer, and etching the photoresist layer to form spaced apart first and second TIV openings in the photoresist layer, where the first TIV opening is wider than the second TIV opening. The method can further include depositing a metal in the first and second TIV openings to form respective first and second TIV structures in contact with the metal line, removing the photoresist layer, forming a high-k dielectric on a top surface of the first and second TIV structures, and depositing a metal layer on the high-k dielectric layer to form respective first and second capacitors.