Embedded MIM Capacitor Die Layout for Package-Level Decoupling
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing on-die decoupling approaches using metal-insulator-metal (MIM) capacitors face deficiencies in high-frequency noise reduction due to die floor planning and area constraints, while package level decoupling capacitors are unsatisfactory in complex die architectures, leading to inadequate power delivery performance.
Innovation Solution
Embedding MIM capacitor dies in package substrates underneath surface mount dies to provide decoupling capacitance, allowing for configurable capacitance and direct connections to power delivery interface circuitry, thereby enhancing power delivery performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If on-die MIM capacitors are used for decoupling, then high-frequency noise is reduced, but die area increases and floor planning becomes constrained
Solution Approach 1:
The patent extracts the MIM capacitor structure from the die itself and places it in the package substrate underneath the die. This separation allows the capacitor to provide decoupling functionality without occupying valuable die area, thus reducing high-frequency noise while maintaining compact die dimensions.
Solution Approach 2:
The solution moves the capacitor from the two-dimensional die plane to the third dimension by embedding it in the package substrate underneath the die. This vertical placement provides additional decoupling capacitance without increasing the die footprint, effectively adding capacitance in the vertical dimension.
2Area of moving object
If package level decoupling capacitors are used, then die area is preserved, but distance and location constraints prevent adequate positioning near PHY blocks
Solution Approach 1:
The patent embeds the MIM capacitor die within the package substrate structure, nesting it underneath the surface-mounted die. This nested configuration allows the capacitor to be positioned in close proximity to the PHY blocks while maintaining a compact overall package footprint.
3Reliability
If die-side capacitors are positioned close to PHY blocks, then power delivery performance improves, but complex die architectures and large single die configurations prevent adequate positioning
Solution Approach 1:
The patent extracts the capacitor from the die structure and relocates it to the package substrate. This extraction resolves the positioning conflict by allowing capacitors to be placed optimally near PHY blocks without being constrained by complex die architectures or large single-die configurations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution improves power delivery performance by providing effective decoupling capacitance close to PHY blocks, reducing AC resonance impedance, and addressing capacitance deficiencies in complex die architectures without increasing die size or cost.
Implementation Method 1
Embedding MIM capacitor dies in package substrates underneath surface mount dies to provide decoupling capacitance
Data Source
AI summary
A package substrate is disclosed. The package substrate includes a die package in the package substrate located at least partially underneath a location of a power delivery interface in a die that is coupled to the surface of the package substrate. Connection terminals are accessible on a surface of the die package to provide connection to the die that is coupled to the surface of the package substrate. Metal-insulator-metal layers inside the die package are coupled to the connection terminals.