Embedded MIM Capacitor Structure for 3D Stack Defect Detection

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Solution Overview

Problem

In 3D integrated circuits and semiconductor packaging, existing technologies face challenges in detecting defects such as passivation cracks, film delamination, and bump-induced damages, which can lead to reduced yield and increased manufacturing costs due to the inability to effectively identify and isolate faulty stacks during the assembly process.

Innovation Solution

The implementation of an embedded metal-isolator-metal (MIM) structure within semiconductor packages, which allows for electrical measurements during the stacking process, enabling the identification of known bad stacks and allowing only known good stacks to proceed, thereby reducing costs and improving yield.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If electrical measurement structures are added to detect defects, then measurement precision improves, but device complexity increases

Engineering Contradiction:
Improvedefect detection capabilityVSAvoidstructure complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The MIM capacitor structure merges the defect detection function with the existing dielectric layer structure. The MIM capacitor is formed by integrating metal electrodes and dielectric materials into the semiconductor package interconnect structure, allowing electrical measurements to be performed without adding separate external sensing components. This combines the structural and sensing functions into a unified system.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The MIM capacitor structure serves multiple functions: it acts as both an electrical measurement sensor for defect detection and as part of the package interconnect structure. The same dielectric layers and metal electrodes that form the capacitor also provide structural support and electrical connectivity, eliminating the need for dedicated sensing components.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Productivity

If electrical measurements are performed during stacking, then productivity improves through real-time defect identification, but device complexity increases due to additional measurement infrastructure

Engineering Contradiction:
Improvemanufacturing efficiencyVSAvoidmeasurement system complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The MIM capacitor structure is formed during the semiconductor fabrication process before final packaging, preparing the measurement infrastructure in advance. This allows electrical measurements to be performed immediately during the stacking process without requiring additional setup or external measurement equipment, enabling real-time defect identification.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The semiconductor package structure itself provides the measurement capability through the embedded MIM capacitor. The dielectric layers and metal electrodes within the package interconnect structure serve as both structural components and sensing elements, allowing the device to self-diagnose defects during stacking without external intervention.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS20240371746A1Semiconductor structure and method of forming the same
Publication Date: 2024.11.07 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20240371746A1 patent drawing
  • US20240371746A1 patent drawing
  • US20240371746A1 patent drawing

AI summary

The present disclosure provides a semiconductor structure, including a capacitor. The capacitor includes a first electrode and a second electrode respectively electrically connected to a first conductor and a second conductor; and a first dielectric layer between the first electrode and the second electrode. In some embodiments, the first dielectric layer contacts with a sidewall surface of the first conductor. The semiconductor structure further includes a second dielectric layer over and adjacent to the capacitor. A method of forming the semiconductor package is also provided.