Embedded Memory-on-Package Layout for Lower Z-Height
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Solution Overview
Problem
Existing Memory on Package (MoP) architectures face challenges with increased Z-height and XY form factor due to tall memory packages and the need for stiffeners, which are often expensive solutions.
Innovation Solution
Embedding memory stacks directly into a mold layer with an opening for compute dies on a package substrate, eliminating the need for a separate memory package substrate and potentially integrating a stiffener within the mold layer to reduce Z-height and XY form factor while maintaining structural integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a tall memory package (stack of memory dies on memory package substrate) is used to achieve MoP architecture, then memory performance and XY footprint are improved, but Z-height increases by 300-350 μm
Solution Approach 1:
The patent transitions from a traditional planar memory package layout to a three-dimensional stacked architecture where memory dies are vertically arranged on the package substrate. This dimensional change allows memory components to occupy vertical space rather than horizontal space, thereby reducing the XY footprint while managing Z-height through alternative packaging approaches.
Solution Approach 2:
The patent embeds the memory die stack within a mold layer that is integrated into the package substrate structure. The memory stack is nested within the substrate's vertical profile rather than protruding externally, allowing the memory components to be contained within the overall package envelope and reducing the effective Z-height of the complete assembly.
2Length of stationary object
If a coreless package architecture is used to mitigate Z-height increase, then Z-height is reduced, but manufacturing cost increases significantly
Solution Approach 1:
The patent divides the package substrate into functional regions: a core region that provides structural support and routing, and peripheral regions that accommodate memory stacks. This segmentation allows the expensive coreless approach to be applied only where necessary for height reduction, while maintaining cost-effective core-based construction in areas where structural integrity and signal routing are priorities, thereby balancing cost and dimensional constraints.
Solution Approach 2:
The patent applies different packaging strategies to different locations on the package substrate. The core region maintains traditional structured construction for cost-effectiveness and structural support, while specific peripheral areas utilize coreless or reduced-height configurations to mitigate overall Z-height. This localized application of quality variations optimizes the trade-off between manufacturing cost and package height.
3Stability of the object's composition
If a stiffener is added to control warpage of package substrate, then structural stability is improved, but XY form factor increases and cost increases
Solution Approach 1:
The patent integrates the stiffener function directly into the mold layer structure that already surrounds and protects the memory die stack. The mold layer is configured to provide both mechanical protection for the embedded memory stack and structural reinforcement to the package substrate, eliminating the need for separate stiffener components and reducing the overall XY form factor.
Solution Approach 2:
The mold layer serves multiple functions simultaneously: it protects the embedded memory die stack, provides structural reinforcement to prevent substrate warpage, and defines the package's external form factor. By making the mold layer multi-functional, the patent eliminates the need for dedicated stiffener components, thereby reducing XY footprint while maintaining warpage control.
4Temperature
If a combination stiffener and integrated heat spreader (IHS) is used to control warpage and improve thermal performance, then thermal performance and warpage control are improved, but cost increases significantly
Solution Approach 1:
The patent combines thermal management and structural reinforcement functions into the existing mold layer and package substrate structure. The mold layer is configured to conduct heat away from the memory die stack while simultaneously providing structural support, eliminating the need for separate IHS and stiffener components and reducing overall manufacturing cost.
Solution Approach 2:
The package substrate and mold layer structure is designed to perform multiple functions: mechanical support, warpage control, and thermal management. The substrate material and mold layer configuration provide both structural integrity and heat dissipation pathways, making specialized IHS components unnecessary and reducing cost while maintaining thermal performance.
Data Source
AI summary
Embodiments disclosed herein include electronic packages. In an embodiment, an electronic package comprises a package substrate with a first memory die stack on the package substrate, and a second memory die stack on the package substrate. In an embodiment, an electrically insulating layer is provided over the first memory die stack and the second memory die stack. In an embodiment, an opening is provided through the electrically insulating layer, and a die module is in the opening over the package substrate.