Embedded MRAM Cell Structure for Compact Memory Arrays
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Solution Overview
Problem
Current magnetic random access memory (MRAM) cells are large, making them unsuitable for applications requiring small form factors, and existing manufacturing techniques expose magnetic tunnel junctions (MTJs) to harsh processes that degrade their performance.
Innovation Solution
The method involves forming MRAM cells with an access transistor and an MTJ on metal interposed-in-interlayer dielectric (ILD) layers, using a hard-to-etch metal layer to define the MRAM area, and embedding MRAM in non-magnetic circuitry to minimize exposure to high temperatures and reduce cell size, with the MTJ being formed on the bottom-most metal layer to avoid degradation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If MRAM cells are built using conventional manufacturing techniques with MTJ on top of all circuitry, then the memory can be fabricated, but the cell size becomes large and the cell height becomes excessive
Solution Approach 1:
The patent segments the manufacturing process into distinct stages: first fabricating non-magnetic circuitry layers, then embedding MTJ structures within interlayer dielectric layers at specific positions. This segmentation allows independent optimization of circuitry and memory elements, reducing overall cell size while simplifying the integration process.
Solution Approach 2:
The patent embeds MTJ structures within interlayer dielectric layers during the fabrication process, nesting the magnetic memory elements inside the existing circuitry architecture. This nesting approach reduces cell height and footprint by utilizing the vertical space within the interlayer dielectric rather than placing MTJ on top of all circuitry.
2Reliability
If MTJ is formed on top of all circuitry layers, then the memory structure can be completed, but the MTJ is exposed to harsh manufacturing processes that degrade its performance
Solution Approach 1:
The patent forms MTJ structures within interlayer dielectric layers during the mid-stage fabrication process, before subsequent high-temperature processing steps are applied to complete the circuitry. This preliminary action protects the MTJ from degradation by ensuring it is already embedded and shielded when harsh processes occur later in manufacturing.
Solution Approach 2:
The interlayer dielectric acts as an intermediary protective layer that shields the embedded MTJ structures from harsh manufacturing processes. By placing MTJ within the dielectric matrix rather than on exposed circuitry surfaces, the dielectric material mediates between the MTJ and harmful environmental factors during subsequent fabrication steps.
3Speed
If SRAM is placed next to logic circuits on the same chip to meet speed requirements, then bandwidth is improved, but the processor size and cost increase
Solution Approach 1:
The patent changes the fundamental parameters of the memory cell structure by using magnetic tunnel junctions with spin transfer torque switching instead of conventional SRAM transistor structures. This parameter change enables much smaller cell sizes while maintaining fast access speeds, allowing high-speed memory to be integrated without proportionally increasing processor area.
Solution Approach 2:
The patent replaces the mechanical/electrical switching mechanism of SRAM transistors with magnetic switching using spin transfer torque in MTJ structures. This substitution enables non-volatile storage with faster access times and smaller footprint, eliminating the need for large SRAM blocks next to logic circuits while maintaining speed requirements.
4Stability of the object's composition
If conventional MRAM cell structures are used, then non-volatile memory functionality is achieved, but the cell size is too large for small form factor applications
Solution Approach 1:
The patent transitions from planar MRAM cell structures to a vertical embedding approach where MTJ structures are placed within interlayer dielectric layers in three-dimensional space. This dimensional change allows the memory cells to utilize vertical space efficiently, achieving non-volatile functionality with dramatically reduced footprint suitable for small form factor applications.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in significantly smaller MRAM cells, reducing switching current requirements and maintaining MTJ integrity by avoiding exposure to high temperatures, thus enabling more compact and efficient magnetic memory arrays.
Implementation Method 1
magnetic storage memory device that is based on spin current-induced-magnetization-switching
Data Source
AI summary
A magnetic random access memory (MRAM) cell includes an embedded MRAM and an access transistor. The embedded MRAM is formed on a number of metal-interposed-in-interlayer dielectric (ILD) layers, which each include metal dispersed there through and are formed on top of the access transistor. A magneto tunnel junction (MTJ) is formed on top of a metal formed in the ILD layers that is in close proximity to a bit line. An MTJ mask is used to pattern the MTJ and is etched to expose the MTJ. Ultimately, metal is formed on top of the bit line and extended to contact the MTJ.