Embedded MRAM Cell Structure for Reduced Footprint
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Solution Overview
Problem
Current magnetic random access memory (MRAM) cells are large, making them unsuitable for applications requiring small form factors, and existing manufacturing techniques expose magnetic tunnel junctions (MTJs) to harsh processes that degrade their performance.
Innovation Solution
The method involves embedding MRAM cells within non-magnetic circuitry using metal-interposed-in-interlayer dielectric (ILD) layers, forming MTJs on top of metal layers closer to the substrate to minimize size and avoid exposure to high temperatures, and using a hard-to-etch metal layer to define the MRAM area, allowing for smaller cell sizes and reduced switching current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If MTJs are built on top of all circuitry using conventional manufacturing techniques, then the MRAM cell structure is complete, but the cell height becomes larger than desired and the cell size increases
Solution Approach 1:
The patent inverts the conventional manufacturing sequence by forming MTJs on lower metal layers (M1-M3) before completing all circuitry layers. This reversal allows MTJs to be embedded within the circuit stack rather than placed on top, reducing cell height and overall device volume while maintaining manufacturing completeness.
Solution Approach 2:
The patent distributes MTJs across multiple vertical levels (different metal layers) rather than confining them to a single top layer. This three-dimensional arrangement reduces the horizontal footprint and allows for more compact cell designs by utilizing the vertical dimension for differentiation.
2Manufacturing precision
If MTJs are exposed to harsh manufacturing processes to ensure complete fabrication, then the manufacturing process is thorough, but the MTJ performance degrades due to high temperature exposure
Solution Approach 1:
The patent performs MTJ formation as a preliminary action on early metal layers (M1-M3) before subsequent high-temperature processing steps occur. By completing critical MTJ fabrication early in the process sequence, the MTJs are protected from degradation by later harsh manufacturing conditions while ensuring complete fabrication of all device components.
Solution Approach 2:
The patent strategically positions MTJs on lower metal layers that are shielded by intermediate layers and structures during subsequent processing. This spatial cushioning protects the sensitive MTJs from direct exposure to high temperatures and harsh chemicals in later manufacturing steps, preserving their performance characteristics.
3Reliability
If standard MRAM cell structures are used, then the memory function is achieved, but the real estate required is too large for small form factor applications
Solution Approach 1:
The patent embeds MTJs within the circuitry stack by nesting them on lower metal layers (M1-M3) that are already present in the CMOS device structure. This nesting approach allows MTJs to occupy space within the existing device footprint rather than requiring additional external area, significantly reducing the overall cell area for small form factor applications.
Solution Approach 2:
The patent transitions from a planar two-dimensional cell layout to a three-dimensional structure by placing MTJs on multiple vertical levels (M1, M2, M3 layers). This vertical differentiation allows for more compact horizontal footprints, reducing the real estate required per cell while maintaining full memory functionality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in significantly smaller MRAM cells, reducing the real estate required and minimizing exposure to detrimental processing temperatures, thereby enhancing the performance and reliability of MRAM cells.
Implementation Method 1
magnetic storage memory device that is based on spin current-induced-magnetization-switching having reduced switching current in the magnetic memory
Data Source
AI summary
A magnetic random access memory (MRAM) cell includes an embedded MRAM and an access transistor. The embedded MRAM is formed on a number of metal-interposed-in-interlayer dielectric (ILD) layers, which each include metal dispersed therethrough and are formed on top of the access transistor. An magneto tunnel junction (MTJ) is formed on top of a metal formed in the ILD layers that is in close proximity to a bit line. An MTJ mask is used to pattern the MTJ and is etched to expose the MTJ. Ultimately, metal is formed on top of the bit line and extended to contact the MTJ.