Embedded MTJ in Interconnects via Dummy Metal Level
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Solution Overview
Problem
The semiconductor industry faces challenges in embedding magnetic tunnel junctions (MTJ) between metal levels in tight pitch interconnects due to vertical dimension constraints and the risk of unwanted interaction with titanium nitride (TiN) during wet cleaning in MRAM device fabrication.
Innovation Solution
A method is developed to insert MTJ between Mx and Mx+2 levels using a MTJ hardmask with a wet clean stop layer, allowing compatibility with small pitch interconnects and TiN metal hardmasks, involving specific steps such as forming a capping layer, filling vias with metals like tungsten or ruthenium, and forming nitride spacers to ensure compatibility and precision.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If MTJ is inserted between metal levels with tight pitch (e.g., 90 nm or 80 nm), then memory cell size is reduced, but vertical dimension constraint prevents insertion between adjacent metal levels (Mx and Mx+1)
Solution Approach 1:
The patent inserts a dummy metal level (Mx+1) between the original Mx and Mx+1 levels, effectively adding a dimensional layer to accommodate the MTJ structure. This allows the MTJ to be positioned between Mx and Mx+2 levels with sufficient vertical spacing (120 nm via height), resolving the vertical dimension constraint while maintaining tight pitch in the horizontal plane.
2Manufacturing precision
If TiN metal hardmask is used for trench and via patterning in tight pitch interconnects, then patterning precision is improved, but wet cleaning after trench etching increases risk of unwanted interaction with MTJ
Solution Approach 1:
The patent introduces a protective capping layer (e.g., silicon nitride or silicon oxide) over the MTJ structure during the wet cleaning process. This intermediary layer prevents direct contact between the wet cleaning chemicals and the MTJ, eliminating unwanted interactions while allowing the TiN hardmask to maintain its patterning precision function.
3Reliability
If MTJ minimum height of 120 nm is required, then MTJ functionality is ensured, but insertion between Mx and Mx+1 levels with 100 nm or 75 nm via height becomes impossible
Solution Approach 1:
The patent segments the interconnect structure by inserting a dummy metal level (Mx+1) between the original Mx and Mx+1 levels. This segmentation creates separate via regions: one from Mx to Mx+1 (120 nm height for MTJ accommodation) and another from Mx+1 to Mx+2 (original via height), allowing the MTJ to achieve its required 120 nm minimum height while maintaining the original tight pitch interconnect architecture.
Data Source
AI summary
Method of forming embedded MRAM in interconnects using a metal hard mask process and the resulting device are provided. Embodiments include forming a first interlayer dielectric (ILD) layer including a first metal (Mx) level; forming a capping layer over the first ILD layer; forming magnetic tunnel junction (MTJ) structures formed in a second ILD over the first capping layer; forming a second metal (Mx+1) level in the second ILD layer; forming a second capping layer over the second ILD layer; and forming a third metal (Mx+2) level in a third ILD layer over the second capping layer.