Embedded NMOS Triggered SCR for Low Clamping Voltage ESD Protection
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Solution Overview
Problem
Conventional Zener-triggered SCR devices consume large silicon real estate and have lower current discharge capacity per unit area, limiting their effectiveness in low-operating power source IC devices and failing to effectively decrease clamping voltage.
Innovation Solution
An embedded N-channel metal oxide semiconductor (NMOS) triggered silicon controlled rectification device is developed, utilizing an NMOSFET and signal detector to decrease clamping voltage and increase the speed of bypassing ESD current without forming an NMOSFET in the path from the anode to the cathode, thereby optimizing silicon usage and enhancing ESD protection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional Zener-triggered SCR devices are used, then ESD protection is provided, but silicon real estate is consumed excessively and current discharge capacity per unit area is reduced
Solution Approach 1:
The device structure is segmented into distinct functional zones: trigger region with NMOSFET, rectifying regions with PIN junctions, and interconnecting doped areas. This segmentation allows each component to be optimized independently, reducing overall device area while maintaining ESD protection functionality.
Solution Approach 2:
The NMOSFET trigger is embedded within the SCR structure, with the trigger region nested inside the rectifying zones. The first P-type heavily doped area is positioned between the trigger and the first N-type heavily doped area, creating a nested configuration that reduces total device footprint.
2Reliability
If conventional SCR devices are used, then ESD protection is provided, but current discharge capacity per unit area is lower
Solution Approach 1:
Heavily doped regions are strategically positioned at critical locations (anode, cathode, and intermediate areas) to enhance local current handling capability. The first P-type heavily doped area and first N-type heavily doped area create high-current paths that increase discharge capacity per unit area.
Solution Approach 2:
The device combines multiple semiconductor material regions (P-type substrate, N-type well, heavily doped P-type and N-type areas) to create a composite structure that optimizes both ESD protection and current discharge capacity. The heterogeneous doping profiles enable simultaneous achievement of high breakdown voltage and high current density.
3Reliability
If PMOSFET is arranged between anode and cathode to increase distance, then turn-on resistance is increased, but clamping voltage is not effectively decreased
Solution Approach 1:
Instead of using PMOSFET as in conventional designs, this invention uses NMOSFET as the trigger device. The NMOSFET is configured with source connected to cathode and drain connected to anode through the first P-type heavily doped area, inverting the conventional arrangement to achieve lower clamping voltage while maintaining high turn-on resistance.
Solution Approach 2:
The device parameters are optimized by adjusting doping concentrations and geometric dimensions. The heavily doped regions reduce series resistance to lower clamping voltage, while the NMOSFET trigger maintains high impedance in the off-state to ensure high turn-on resistance. This parameter optimization simultaneously addresses both requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The NMOS triggered silicon controlled rectification device effectively decreases clamping voltage and increases the speed of ESD current bypassing, addressing the limitations of conventional SCR devices while supporting low-voltage applications without increasing turn-on resistance.
Implementation Method 1
Electrostatic Discharge (ESD) damage has become the main reliability issue for CMOS IC products fabricated in the nanoscale CMOS processes
Implementation Method 2
a first N-type heavily doped area arranged in the P-type substrate and electrically connected to the cathode; an N-type well arranged in the P-type substrate; and a first P-type heavily doped area arranged in the N-type well and electrically connected to the anode
Data Source
AI summary
An embedded NMOS triggered silicon controlled rectification device includes a P-type substrate, at least one rectifying zone, and at least one trigger. The rectifying zone includes a first N-type heavily doped area, an N-type well, and a first P-type heavily doped area. Alternatively, the device includes an N-type substrate, a first P-type well, at least one rectifying zone, and at least one trigger. The rectifying zone includes a second P-type well, a first N-type heavily doped area, and a first P-type heavily doped area. The trigger cooperates with the P-type substrate or the first P-type well to form at least one NMOSFET. The trigger is independent to the rectifying zone. The first P-type heavily doped area is arranged between the trigger and the first N-type heavily doped area.