Embedded NVM in HKMG Process via Gate-Last Integration
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Solution Overview
Problem
Conventional methods face challenges in integrating non-volatile memory devices, such as flash EEPROM, into standard CMOS processes, especially when replacing silicon dioxide gate dielectrics and polysilicon gate conductors with high-k dielectrics and metal gate electrodes, as existing HKMG fabrication processes can destroy charge storage elements during planarization.
Innovation Solution
A compact split-gate poly EEPROM bitcell is integrated with high-k metal gate CMOS transistors using a CMOS gate-last fabrication sequence, forming planarized dielectric layers and selectively removing sacrificial poly gate electrodes to form CMOS gate electrode openings for high-k metal gate electrode formation, while protecting flash cell components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional HKMG fabrication processes are used to replace silicon dioxide gate dielectrics and polysilicon gate conductors with high-k dielectrics and metal gate electrodes, then transistor performance is improved, but charge storage elements are destroyed during planarization
Solution Approach 1:
The patent divides the wafer into distinct regions: flash memory cell regions where polysilicon gate structures are retained and preserved, and CMOS transistor regions where sacrificial polysilicon gates are removed to allow HKMG formation. This spatial segmentation enables different device types to coexist on the same wafer with different gate structures, allowing transistor performance improvement in CMOS regions without damaging flash memory charge storage elements.
Solution Approach 2:
The patent applies different gate structure treatments to different locations on the wafer. In CMOS transistor regions, high-k dielectric and metal gate electrode layers are formed to improve transistor performance. In flash memory cell regions, the original polysilicon gate structures are preserved to maintain charge storage functionality. This local differentiation resolves the contradiction by tailoring the gate structure to the specific functional requirements of each device type.
2Adaptability or versatility
If embedded non-volatile memory is integrated into CMOS devices, then single chip functionality is improved, but process compatibility challenges arise
Solution Approach 1:
The patent employs a universal fabrication process that can produce both flash memory devices and CMOS transistors on the same wafer using shared process steps such as dielectric layer deposition, patterning, and etching. The process is designed to be multi-functional, accommodating different device architectures (preserved polysilicon gates for flash, removed sacrificial gates for CMOS-HKMG) within a single manufacturing flow, thereby improving single-chip functionality while maintaining process compatibility.
Solution Approach 2:
The patent uses sacrificial polysilicon gate structures that are formed in advance during the common fabrication process. These sacrificial gates serve as placeholders that guide subsequent processing steps. In CMOS regions, they are later removed to enable HKMG formation, while in flash regions, they are preserved as functional gates. This preliminary action enables process compatibility by providing a unified starting point for both device types.
Data Source
AI summary
A process integration is disclosed for fabricating complete, planar non-volatile memory (NVM) cells (110) prior to the formation of high-k metal gate electrodes for CMOS transistors (212, 213) using a planarized dielectric layer (26) and protective mask (28) to enable use of a gate-last HKMG CMOS process flow without interfering with the operation or reliability of the NVM cells.