Embedded Non-Volatile Memory Using Single Polysilicon Layer
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Solution Overview
Problem
Existing non-volatile memory devices (NVM) integrated into System-on-Chip (SoC) require complex control circuitry and high voltage values, increasing design complexity and manufacturing costs due to the use of floating gate transistors that deviate from standard CMOS processes.
Innovation Solution
A non-volatile memory device with a matrix of memory cells featuring a shared electrically floating layer for capacitive coupling, allowing reduced voltage operations and simplified control structures, utilizing a single polysilicon layer within standard CMOS technology, enabling efficient programming and erasing through Fowler-Nordheim tunneling and band-to-band tunneling-induced hot electron mechanisms.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If floating gate transistors are used to create non-volatile memory cells, then programming and erasing operations can be performed, but device complexity and manufacturing cost increase due to additional polysilicon layers and deviation from standard CMOS processes
Solution Approach 1:
The patent extracts the floating gate functionality from the transistor structure and implements it as a separate capacitive structure. The memory cell uses a standard CMOS transistor coupled with a capacitor that has a floating gate, separating the storage function from the switching function. This eliminates the need for complex floating gate transistors while maintaining non-volatile storage capability.
Solution Approach 2:
The patent makes the single polysilicon layer serve multiple functions: it forms both the control gate of the MOS transistor and the floating gate for charge storage. This multi-functionality eliminates the need for additional polysilicon layers and simplifies the manufacturing process to standard CMOS compatibility.
2Reliability
If floating gate transistors are used for non-volatile memory, then data can be stored non-volatily, but manufacturing cost increases due to additional polysilicon layers
Solution Approach 1:
The patent makes the single polysilicon layer serve multiple functions: it forms both the control gate of the MOS transistor and the floating gate for charge storage. This multi-functionality eliminates the need for additional polysilicon layers and simplifies the manufacturing process to standard CMOS compatibility.
Solution Approach 2:
The patent merges the control gate and floating gate structures into a single integrated unit. The control capacitor shares the floating gate electrode with the storage transistor, combining what would traditionally be separate components into a unified structure that reduces manufacturing steps and material requirements.
3Reliability
If complex control circuitry is used to generate high voltages for memory operations, then programming and erasing can be performed, but device area increases
Solution Approach 1:
The patent extracts the high voltage generation requirement from the memory cell operation and implements it externally through voltage multiplier circuits connected to the bit lines and word lines. This allows the memory cells themselves to operate at lower voltages, reducing the area needed for control circuitry within the memory array.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a compact, simply addressable memory device with reduced voltage requirements, simplifying the control structure and lowering manufacturing costs while maintaining high reliability and data retention, with improved efficiency in programming and erasing operations.
Implementation Method 1
The electrically floating layer provides a first capacitive coupling with the read portion and a second capacitive coupling with the control portion
Implementation Method 2
erasable through fowler-nordheim tunneling
Implementation Method 3
The read portion is configured to be traversed by or have an electrical current flow therethrough indicative of a logic value stored in the memory cell
Data Source
AI summary
A non-volatile memory includes a plurality of memory cells arranged in a plurality of rows and columns. Each memory cell includes a read portion and a control portion. The read portion and the control portion share an electrically floating layer of conductive material defining a first capacitive coupling with the read portion and a second capacitive coupling with the control portion. The first capacitive coupling defines a first capacity greater than a second capacity defined by the second capacitive coupling. The control portion is configured so that an electric current injects or extracts charge carriers into or from the electrically floating layer to store of a first logic value or a second logic value, respectively, in the memory cell.