Embedded Electronic Package With Blind Vias to Block Circuit Voids
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Solution Overview
Problem
Conventional semiconductor packages face challenges in increasing functionality while maintaining reliability, due to the need for multiple semiconductor chips on a single through-silicon interposer, which results in lower process yield and reliability due to increased routing layers.
Innovation Solution
The electronic package design includes an encapsulation layer with a protective and insulating layer structure, featuring blind vias and a circuit layer that electrically connects to the electronic structure, preventing voids from transferring to the insulating layer and improving yield and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple semiconductor chips are arranged on a single through-silicon interposer to increase functionality, then the function of the semiconductor package is improved, but the number of routing layers increases causing lower process yield and reliability
Solution Approach 1:
The patent transitions from a planar routing architecture to a three-dimensional architecture by embedding the electronic structure within the encapsulation layer and using blind vias to connect circuit layers. This vertical integration approach allows multiple chips to be connected without proportionally increasing the number of horizontal routing layers, thereby maintaining process yield while achieving enhanced functionality.
Solution Approach 2:
The electronic structure is embedded within the encapsulation layer, with circuit layers nested above and conductive elements nested within blind vias. This nested configuration allows multiple functional elements to be integrated in a compact vertical arrangement, reducing the need for extensive lateral routing and associated routing layers.
2Quantity of substance
If the number of routing layers is increased to accommodate multiple chips, then more chips can be connected, but the process yield decreases
Solution Approach 1:
The patent utilizes the vertical dimension by forming blind vias that extend from the circuit layer into the encapsulation layer to reach conductive elements. This vertical connectivity approach enables multiple chips to be interconnected through the third dimension rather than requiring additional horizontal routing layers, thus maintaining high process yield while increasing the number of connected chips.
Solution Approach 2:
The encapsulation layer serves as an intermediary medium that houses the electronic structure and provides a substrate for embedding conductive elements. This intermediary structure facilitates vertical electrical connections between circuit layers and chips without requiring additional routing layers, thereby preserving process yield while enabling multi-chip integration.
3Adaptability or versatility
If more routing layers are used to connect chips, then functionality increases, but reliability of electrical connection decreases
Solution Approach 1:
The patent implements vertical electrical connections through blind vias that penetrate the encapsulation layer, establishing direct conductive pathways between circuit layers and embedded chips. This three-dimensional connection approach reduces the number of lateral routing interfaces, thereby minimizing potential failure points and improving electrical connection reliability while maintaining enhanced functionality.
Solution Approach 2:
The patent extracts the electronic structure from the traditional planar routing architecture and embeds it within the encapsulation layer. This separation allows electrical connections to be established through vertical blind vias rather than through multiple horizontal routing layers, reducing connection complexity and improving reliability while preserving functionality.
Data Source
AI summary
An electronic package is provided, in which an electronic structure is embedded in an encapsulation layer, a protective layer is formed on the encapsulation layer, an insulating layer is formed on the protective layer, and at least one blind via is formed penetrating through the insulating layer and the protective layer, so that the electronic structure is exposed from the blind via to make a circuit layer formed on the insulating layer extending into the blind via to electrically connect the electronic structure. Therefore, by the double layer design of the insulating layer and the protective layer, voids generated by the process are free from being transferred to the insulating layer to avoid the voids remaining in the circuit layer.