Embedded Package Core Cavity Alignment for Semiconductor Integration
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Solution Overview
Problem
Current embedded packages face challenges in efficiently integrating semiconductor chips with varying orientations and dimensions within a substrate, leading to issues with alignment and insulation layer formation, which affects the exposure of bumps and pads for effective electrical connections.
Innovation Solution
The proposed solution involves a core layer with a cavity, where semiconductor chips with bumps and pads are stacked at different orientations, covered by an insulation layer with strategically formed openings to expose these features, ensuring equal depth and alignment for efficient electrical coupling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If semiconductor chips with varying orientations and dimensions are integrated in a substrate, then device functionality is improved, but alignment precision and insulation layer formation deteriorate
Solution Approach 1:
The patent divides the substrate into multiple cavity regions, each capable of holding semiconductor chips with different orientations and dimensions. The insulation layer is segmented into multiple opening regions corresponding to different chip types, allowing each region to be optimized independently for its specific chip configuration while maintaining overall manufacturing precision
Solution Approach 2:
The patent implements local quality by creating different cavity configurations and opening depths in different regions of the substrate. Each region is tailored to accommodate specific chip orientations and dimensions, with insulation layer openings adjusted locally to ensure precise exposure of bumps and pads for each chip type
2Reliability
If insulation layer openings are formed to expose bumps and pads, then electrical connectivity is improved, but warping risk increases
Solution Approach 1:
The patent controls the depth parameter of insulation layer openings to precisely expose bumps and pads without excessive removal. By optimizing opening depth as a critical parameter, the patent ensures adequate electrical connectivity while minimizing structural disruption that could cause warping
Solution Approach 2:
The patent performs preliminary positioning and alignment of semiconductor chips in cavities before forming the insulation layer openings. This preliminary action ensures that bumps and pads are correctly positioned, allowing openings to be formed with minimal material removal and reduced warping risk
Data Source
AI summary
An embedded package includes a core layer having a cavity, a first semiconductor chip disposed in the cavity, and bumps disposed on a top surface of the first semiconductor chip, a second semiconductor chip disposed on the first semiconductor chip and the core layer, pads disposed on a top surface of the second semiconductor chip, and a first insulation layer disposed on the core layer and the first and second semiconductor chips. The first insulation layer has first openings that expose the bumps and second openings that expose the pads, and the first and second openings have a similar depth.