Embedded Semiconductor Package With Dielectric Liner Isolation
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Solution Overview
Problem
Conventional semiconductor packaging solutions, such as lead frame and metal clip based packages, have reached physical limits in terms of power loss, current density, and efficiency, particularly due to soldered connections that impose practical limitations.
Innovation Solution
A semiconductor assembly with a package substrate featuring an interior laminate layer, metallization layers, and semiconductor dies embedded within, where dielectric material liners are used to enhance voltage breakdown resistance and electrical isolation, allowing for improved power handling and efficiency in a compact form factor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional lead frame and metal clip based semiconductor packages are used, then electrical interconnections can be established, but power loss increases and current density decreases due to soldered connection limitations
Solution Approach 1:
The patent extracts and eliminates the soldered connection structure from the semiconductor package, replacing it with direct bonding technology. This removal of the harmful soldered connection element directly reduces power loss and eliminates the associated limitations on current density and efficiency.
Solution Approach 2:
The patent replaces the mechanical soldered connection system with a direct bonding system that uses metallization layers and dielectric liners. This substitution eliminates the mechanical limitations of solder joints, enabling improved power handling, higher current density, and better thermal management without the energy losses associated with soldered connections.
2Productivity
If soldered connections are used in semiconductor packages, then electrical interconnections are established, but efficiency decreases due to practical limitations of soldered connections
Solution Approach 1:
The patent extracts and eliminates the soldered connection structure from the semiconductor package, replacing it with direct bonding technology. This removal of the harmful soldered connection element directly reduces power loss and eliminates the associated limitations on current density and efficiency.
Solution Approach 2:
The patent replaces the mechanical soldered connection system with a direct bonding system that uses metallization layers and dielectric liners. This substitution eliminates the mechanical limitations of solder joints, enabling improved power handling, higher current density, and better thermal management without the energy losses associated with soldered connections.
3Power
If conventional semiconductor packaging is used, then manufacturing can be performed with existing processes, but power handling capability is limited due to physical limits of conventional solutions
Solution Approach 1:
The patent segments the semiconductor package into distinct functional layers: semiconductor dies, metallization layers, dielectric liners, and encapsulant material. This segmentation allows each layer to be optimized independently for power handling while using established manufacturing processes for each material type, making the advanced design manufacturable with existing technology.
Solution Approach 2:
The patent employs composite material structures combining semiconductor dies, conductive metallization layers, insulating dielectric liners, and protective encapsulant materials. This composite approach enables superior power handling capability by leveraging the strengths of each material while maintaining compatibility with conventional manufacturing processes for each material type.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances voltage breakdown characteristics, mitigates electromigration, and improves thermal and electrical conduction, resulting in a more robust and efficient power stage circuit with increased current density and reduced power loss.
Implementation Method 1
a liner of dielectric material on the first semiconductor die... the liner of dielectric material is disposed on a corner of the first semiconductor die that is between the first and second load terminals
Data Source
AI summary
A method of forming a semiconductor package includes producing a package substrate that includes an interior laminate layer, a first metallization layer disposed below the interior laminate layer, and a second metallization layer disposed above the interior laminate layer, providing a first load terminal on a first surface of the first semiconductor die and a second load terminal on a second surface of the first semiconductor die; and a liner of dielectric material on the first semiconductor die; providing a liner of dielectric material on the first semiconductor die; embedding the first semiconductor die within the interior laminate layer such that the first surface of the first semiconductor die faces the second metallization layer, and wherein the liner of dielectric material is disposed on a corner of the first semiconductor die that is between the first and second load terminals of the first semiconductor die.