Embedded Package Insulation Thickness for Parasitic Capacitance

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Solution Overview

Problem

The existing embedded semiconductor packages face challenges in achieving high-speed operation due to large parasitic capacitance caused by the short distance between the semiconductor chip's active region and the circuit wiring line, which is exacerbated by the need for miniaturization and compactness, and increasing the bump height leads to potential short-circuiting between adjacent bumps.

Innovation Solution

The embedded package design includes a semiconductor chip divided into cell and peripheral regions, with an insulation member in the cell region having a thickness greater than the bump height, and in the peripheral region, the insulation member's thickness is either identical to or less than the bump height, featuring a straight, acute, step-like, or curved slope, allowing for increased distance between the chip and circuit wiring line while preventing short-circuiting.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Volume of moving object

If the distance between the semiconductor chip and circuit wiring line is shortened to achieve miniaturization, then the package size is reduced, but parasitic capacitance increases

Engineering Contradiction:
Improvepackage sizeVSAvoidparasitic capacitance
Core Design Contradiction:
Volume of moving objectVSObject-generated harmful factors

Solution Approach 1:

The patent applies local quality by creating different insulation member thicknesses in different regions: the cell region has a greater thickness than the bump height, while the peripheral region has a thickness equal to or less than the bump height. This localized differentiation allows the cell region to maintain larger spacing for reduced parasitic capacitance while the peripheral region accommodates bump structures, achieving both miniaturization and low parasitic capacitance.

Inventive Principle:
Principle #3Local quality

2Object-generated harmful factors

If the bump height is increased to lengthen the distance between chip and wiring line, then parasitic capacitance is reduced, but adjacent bumps may short-circuit

Engineering Contradiction:
Improveparasitic capacitanceVSAvoidshort-circuit prevention
Core Design Contradiction:
Object-generated harmful factorsVSReliability

Solution Approach 1:

The patent resolves this contradiction by applying local quality through region-specific insulation thickness design. The cell region insulation member has greater thickness than the bump height, providing sufficient spacing to reduce parasitic capacitance without requiring increased bump height. This eliminates the short-circuit risk while achieving low parasitic capacitance performance.

Inventive Principle:
Principle #3Local quality

3Reliability

If the insulation member thickness is uniformly increased to prevent short-circuiting, then reliability is improved, but package size increases

Engineering Contradiction:
Improveshort-circuit preventionVSAvoidpackage size
Core Design Contradiction:
ReliabilityVSVolume of moving object

Solution Approach 1:

The patent applies local quality by differentiating insulation member thickness across regions: the cell region has greater thickness than bump height for reliability, while the peripheral region has thickness equal to or less than bump height to minimize package size. This localized approach achieves both reliability and compactness.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent utilizes vertical dimensionality by varying insulation member thickness in the vertical direction across different horizontal regions. This three-dimensional configuration allows the insulation member to provide sufficient spacing where needed (cell region) while maintaining compact overall package dimensions through optimized thickness distribution.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS9111820B2Embedded package and method for manufacturing the same
Publication Date: 2015.08.18 SK HYNIX INC
  • US9111820B2 patent drawing
  • US9111820B2 patent drawing
  • US9111820B2 patent drawing

AI summary

An embedded package includes a semiconductor chip divided into a cell region and a peripheral region, having a first surface and a second surface which faces away from the first surface, and including an integrated circuit which is formed in the cell region on the first surface, a bonding pad which is formed in the peripheral region on the first surface and a bump which is formed over the bonding pad; a core layer attached to the second surface of the to semiconductor chip; an insulation component formed over the core layer including the semiconductor chip and having an opening which exposes the bump; and a circuit wiring line formed over the insulation component and the bump and electrically connected to the bump, wherein the insulation component formed in the cell region has a thickness larger than a height of the bump.