Embedded Package Connection Joint Group Design
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Solution Overview
Problem
Existing semiconductor packages face challenges in withstanding external stresses, leading to cracks in connection joints, which affects their endurance and package density due to the scaling down of electronic systems and the demand for multi-functional and large memory packages.
Innovation Solution
The proposed embedded package design includes a first semiconductor chip embedded in a package substrate with a second semiconductor chip mounted on the surface, and a plurality of external connection joints densely aggregated in a joint region spaced apart from the second semiconductor chip's sidewall, enhancing endurance against physical and thermal stresses while allowing for increased package density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If connection joints are arrayed along a rectangular line on the package substrate, then electrical connection is achieved, but cracks occur in the connection joints due to external stresses and physical shocks
Solution Approach 1:
The patent applies local quality by creating a joint region with different properties from the rest of the substrate. The joint region has a specific geometry (concave or convex) that locally modifies the stress distribution characteristics, making this specific area more resistant to crack propagation while maintaining standard connection joint functionality.
Solution Approach 2:
The patent implements beforehand cushioning by designing the joint region geometry in advance to prevent crack formation. The concave or convex structure acts as a stress buffer that absorbs and redistributes external stresses and physical shocks before they can propagate through the connection joints, thereby preventing crack initiation and propagation.
2Weight of moving object
If electronic systems are scaled down to be lighter and smaller, then portability is improved, but package density must be increased to maintain functionality
Solution Approach 1:
The patent applies dimensionality change by utilizing the vertical dimension through stacked package architecture. Multiple semiconductor chips are stacked vertically and connected through through-silicon vias (TSVs), enabling increased package density without increasing the horizontal footprint, thus supporting miniaturized electronic systems.
Solution Approach 2:
The patent implements nesting by embedding passive devices within the substrate and stacking active devices vertically. The embedded passive devices are nested within the substrate volume, while multiple active chips are nested in a vertical stack, maximizing the use of three-dimensional space to achieve higher package density in a smaller overall package.
3Quantity of substance
If multiple semiconductor chips are placed in a single package, then package density is increased, but external stresses cause cracks in connection joints
Solution Approach 1:
The patent applies segmentation by dividing the package into distinct functional regions: joint regions for connection joints and chip mounting regions for semiconductor chips. This spatial segmentation allows the joint regions to be optimized for stress resistance while chip regions are optimized for device placement, enabling high package density without compromising connection joint reliability.
Solution Approach 2:
The patent implements local quality by giving specific geometric characteristics to the joint region that differ from the chip mounting region. The joint region's concave or convex geometry provides localized stress management capabilities, allowing the package to accommodate multiple chips at high density while maintaining crack resistance in the connection areas.
4Quantity of substance
If connection joints are densely aggregated, then pitch size is reduced and package density is increased, but crack susceptibility increases under external stresses
Solution Approach 1:
The patent applies local quality by creating a joint region with specialized geometry that locally enhances stress resistance. Within this designated joint region, connection joints can be densely aggregated with reduced pitch size while the region's geometric features (concave or convex) provide localized stress distribution that prevents crack propagation even at high density.
Solution Approach 2:
The patent implements beforehand cushioning by designing the joint region geometry in advance to buffer stresses before they reach the densely aggregated connection joints. The geometric features of the joint region act as a protective buffer that redistributes external stresses, allowing high-density joint aggregation without increasing crack susceptibility.
Data Source
AI summary
An embedded package includes a first semiconductor chip embedded in a package substrate, a second semiconductor chip disposed over a first surface of the package substrate, and a group of external connection joints disposed on the first surface of the package substrate and between a sidewall of the second semiconductor chip and an edge of the embedded package. Related memory cards and related electronic systems are also provided.