Embedded Semiconductor Package with Pre-formed Conductive Pillars

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Solution Overview

Problem

The manufacturing process of embedded semiconductor packages is complex, leading to low product yield and high costs due to the need for prepreg lamination and laser drilling for through-via structures or redistribution layers (RDLs).

Innovation Solution

A semiconductor package structure featuring a conductive base, semiconductor die, and conductive pillars surrounded by an encapsulant, where the conductive pillars are formed before encapsulation, eliminating the need for costly through-via structures or RDLs, and using a molding process for encapsulant formation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If through-via structures or redistribution layers (RDLs) are used in embedded semiconductor packages, then electrical transmission performance is improved, but manufacturing complexity increases and product yield decreases

Engineering Contradiction:
Improveelectrical transmission performanceVSAvoidmanufacturing process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The conductive pillars are formed before the encapsulant is applied, establishing the electrical transmission path in advance. This preliminary formation of conductive structures eliminates the need for subsequent complex through-via drilling or RDL formation steps, thereby maintaining electrical performance while simplifying the overall manufacturing process

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent extracts and eliminates the complex through-via and RDL structures from the manufacturing process by using pre-formed conductive pillars that are directly embedded in the encapsulant. This removal of unnecessary intermediate structures reduces manufacturing complexity while preserving the essential electrical transmission function

Inventive Principle:
Principle #2Taking out (Extraction)

2Reliability

If through-via structures or redistribution layers (RDLs) are used in embedded semiconductor packages, then electrical transmission performance is improved, but manufacturing cost increases

Engineering Contradiction:
Improveelectrical transmission performanceVSAvoidmanufacturing cost
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The conductive pillars are formed as simple, cost-effective structures using basic semiconductor fabrication techniques rather than expensive laser drilling or multiple lamination steps. These pillars serve their purpose effectively as part of the encapsulation process, reducing overall manufacturing costs while maintaining electrical performance

Inventive Principle:
Principle #27Cheap short-living objects (Disposable)

3Reliability

If known good dies are used during assembly, then product quality is improved, but risk of damage during complex assembly processes increases

Engineering Contradiction:
Improveproduct qualityVSAvoidassembly process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The conductive pillars and their electrical connections are prepared in advance before the known good dies are attached to the substrate. This preliminary preparation of the electrical transmission path simplifies the assembly process, reducing handling steps and minimizing the risk of damaging valuable known good dies during assembly

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS11437247B2Semiconductor package structure and method for manufacturing the same
Publication Date: 2022.09.06 ADVANCED SEMICON ENG INC
  • US11437247B2 patent drawing
  • US11437247B2 patent drawing
  • US11437247B2 patent drawing

AI summary

A semiconductor package structure and a method of manufacturing a semiconductor package structure are provided. The semiconductor package structure includes a conductive base, a first semiconductor die, a first conductive pillar, and a first encapsulant. The conductive base has a first surface. The first semiconductor die is disposed on the first surface of the conductive base. The first conductive pillar is disposed on the first semiconductor die. The first encapsulant is disposed on the first surface of the conductive base. The first encapsulant encapsulates the first semiconductor die. The first encapsulant includes an opening defined by the first conductive pillar.