Embedded Power Package Shielding Pad for Switching Noise Isolation
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Solution Overview
Problem
Conventional semiconductor packaging solutions for power stage circuits face limitations in power loss, current density, and efficiency, particularly due to soldered connections, which hinder high performance and compact design.
Innovation Solution
A semiconductor package design featuring a laminate package substrate with embedded power transistor and driver dies, incorporating a shielding pad in the metallization layer to shield I/O routings from switching signal interference, enhancing electrical and thermal performance while maintaining a small footprint.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional semiconductor packaging solutions with soldered connections are used, then manufacturing robust electrical interconnections is achieved, but power loss increases and current density decreases
Solution Approach 1:
The patent extracts and eliminates the soldered connection layer from the electrical interconnection path. By using direct copper-to-copper bonding between the lead frame and substrate, the solder joint is removed entirely, eliminating the associated power losses and manufacturing limitations while maintaining robust electrical connections
Solution Approach 2:
The patent replaces the mechanical soldering process with a direct metallurgical bonding system. The copper interconnect structure enables direct bonding between components without requiring solder materials or soldering processes, substituting a more efficient electrical-metallurgical connection method
2Quantity of substance
If conventional semiconductor packaging solutions are used, then electrical interconnections are established, but current density is limited
Solution Approach 1:
The patent transitions from two-dimensional planar interconnections to three-dimensional vertical stacking. Multiple copper layers are stacked vertically within the substrate, creating multiple current paths and significantly increasing the effective cross-sectional area for current flow, thereby enabling higher current density
Solution Approach 2:
The patent employs a composite structure combining copper interconnect layers with a substrate material that provides both mechanical support and electrical pathways. This composite approach enables optimized current distribution and higher current density through the integrated material system
3Area of stationary object
If compact packaging design is implemented, then areal footprint is reduced, but signal interference between I/O routings and switching signals increases
Solution Approach 1:
The patent introduces a ground plane as an intermediary shielding layer positioned between the I/O routings and the switching signal traces. This ground plane acts as an electromagnetic shield, blocking capacitive coupling and noise interference while allowing the compact layout to be maintained
Solution Approach 2:
The patent applies differential impedance control and localized grounding specifically to the I/O routing regions that are in close proximity to switching signals. By optimizing the local electromagnetic environment in these critical areas, signal integrity is maintained despite the compact overall package size
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design achieves low power loss, high current density, and efficient signal integrity by mitigating capacitive coupling, allowing for compact and robust electrical interconnections.
Implementation Method 1
a shielding pad formed in the first outer metallization layer that is configured to electrically shield at least one of the I/O routings from the switching signal pad during operation of the first and second power transistor dies
Data Source
AI summary
A semiconductor package includes a laminate package substrate, first and second power transistor dies embedded within the laminate package substrate, a driver die embedded within the laminate package substrate, a plurality of I/O routings electrically connected with I/O terminals of the driver die, a switching signal pad electrically connected with a second load terminal of the first power transistor die and a first load terminal of the second power transistor die, and a shielding pad that is configured to electrically shield at least one of the I/O routings from the switching signal pad during operation of the first and second power transistor dies, wherein the shielding pad is exposed from the electrically insulating layer.